# How to prevent high side PMOS from glitching?

I want to use a PMOS-Transistor as a high side switch like so:

simulate this circuit – Schematic created using CircuitLab

But when I tested this circuit on a breadboard, there was always a small voltage spike at the output, when the 12V where switched on. Since this will be used as a control signal to external devices it must not glitch when powered on.

Is there anything I can do to improve this circuit? Or are PMOS-Transistors entirely unsuitable for this purpose. I already thought about using NMOS instead, but then I would have to add a charge pump to get above 12V which would add an undesirable amount of cost and complexity.

Since I do not have to source a lot of current (/the voltage drop is not that relevant), would it help to use BJTs instead?

UPDATE:

I did some more measurements and the amplitude and duration of the spike is proportional to the load resistance. Removing M2 did not change the result.

This means that this is not a suitable solution for me because the load resistance can be very high. With R_Load > 10k the output voltage does not even go down to 0V.

So the real question seems to be: what are the alternatives? BJTs?

UPDATE 2:

The question is not why this happens (I know it happens because it takes a few microseconds to charge the gate), but how to prevent it. Another PMOS transistor will not help, because it could make the problem less severe, but it will still be there. Especially with light loads.

So again my question: Can I somehow make this better? What happens if I replace M1 with a PNP-Transistor and a base resistor (I don't have one to test at the moment)?

• What helps if you understand what causes the glitch instead of trying whatever is possible. Very likely the voltage spike is caused by a combination of fast switching and Gate-Drain and Gate-Source capacitances of the NMOS transistors. If you switch on M2 the gate of M1 is abruptly connected to ground. I would add a series resistor of 1 kohm with the gate of M1 so that its gate cannot discharge/charged so quickly and see if that fixes the problem. – Bimpelrekkie Dec 5 '16 at 13:54
• @FakeMoustache: I think I know what causes the glitch. It has nothing to do with M2. I think rDS of M1 is low until the gate of M1 is charged to the same voltage as source. – Karsten Dec 5 '16 at 14:01
• Describe the voltage spike or better still, take a picture and post it. Fully describe the load conditions, the length of wires and the power supply too. All potential contributory factors. – Andy aka Dec 5 '16 at 14:06
• OP - FakeM is telling you why M1's gate is low - M2's drain-source capacitance is pulling M1's gate down for whatever period it takes R1 to charge it up. I'm 99.9% certain that if you disconnect M2 then you won't see any power-on glitch. – brhans Dec 5 '16 at 14:17
• The circuit will only work properly if M1 is a PMOS and M2 is an NMOS. My suggestion was to add a gate resistor to PMOS M1. – Bimpelrekkie Dec 5 '16 at 15:21