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I'm working on a project and try to design a layout using cmos CAD tool Magic. In a part of the project, I connect the nmos transistors in the form of shared diffusion as follows(each square represents 90nm x 90nm block):

enter image description here

There are four parallel transistors there. All drains and sources connected together. Drains connected to output Q and sources go to GND.

And when I extract the layout as spice, the part corresponds to the part of the layout above is like this:

M1004 GND A Q Gnd nfet w=0.36u l=0.18u
+ ad=0.3888p pd=3.6u as=0.5184p ps=5.04u 
M1005 Q B GND Gnd nfet w=0.36u l=0.18u
+ ad=0p pd=0u as=0p ps=0u 
M1006 GND C Q Gnd nfet w=0.36u l=0.18u
+ ad=0p pd=0u as=0p ps=0u 
M1007 Q D GND Gnd nfet w=0.36u l=0.18u
+ ad=0p pd=0u as=0p ps=0u

My question is, why all the AD PD AS PS dimensions are extracted as 0? Is it an error that shows up in all cmos CAD tools or am I doing something wrong with Magic? Or is this the correct form of representing shared diffusion contacts in SPICE that I shouldn't be worrying about?

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Eventually I found out that in SPICE tools the AD AS PD PS values are calculated node by node. Like, if there are more than one transistor terminal connected to a node, the SUM of all corresponding perimeter/area values are calculated for that node.

So in my case since all the transistors are in parallel, all perimeter/area values corresponds to the sources(and drains at the other node) are summed up and written by the first transistor. The result would be the same if they were written seperately. So it is not an error or bug that Magic does.

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