I am trying to build a simple JFET common source amplifier to get about 5-10 times gain for a signal I have coming from a microphone with an amplifier already in it, from ADA Fruit, here

I am working with a circuit just like below, but with the capacitor on the output removed.

enter image description here

I have tried various values, but currently I have RD at 10 KΩ, RS at 1 KΩ, Cs and Cin are are .1 μF, and RG is 1 MΩ. VDD is 5 volts. I tried two different transistors FQP30N06L here and J310 here. From what I understand, this should give a gain of 10x.

I can generate a signal by whistling, and the preamp on my circuit gives about 100-500 mV sine wave output. However, my output signal from the drain is always smaller than my input signal.

I am not sure what is wrong here, any advice would be appreciated :)

  • \$\begingroup\$ What is the part number of the JFET? \$\endgroup\$ Dec 6, 2016 at 3:31
  • \$\begingroup\$ I just updated my post with the part numbers \$\endgroup\$
    – Alex K
    Dec 6, 2016 at 3:33
  • 5
    \$\begingroup\$ What DC voltage do you measure on the drain? 5V may not be enough to supply a JFET amplifier - their characteristics vary greatly between units and it is quite possible that the device is saturated. The FQP30N06L is completely unsuitable as it is an enhancement device. \$\endgroup\$ Dec 6, 2016 at 4:06
  • \$\begingroup\$ That's Kevin. I'm still learning the difference between all the types of FETs. I had the enhancement mode device available, but didn't realize it wasn't suitable. Thanks for the tip. \$\endgroup\$
    – Alex K
    Dec 6, 2016 at 17:15

3 Answers 3


If you leave Cs out then you are correctly expecting a gain of 10 in the Common Source configuration you show. But the resistor values and devices you have selected will prevent a successful result. The FQP30N06L is an enhancement mode device and won't work at all in this bias configuration.
The J310 is enhancement mode (the right type of device), but the VGs(off) and 0-VGS(IDSS) is too high to work in this configuration with this supply voltage and resistor values. You should read this to help your understanding: http://www.vishay.com/docs/70595/70595.pdf

Your biasing is this type: enter image description here

In this configuration Rs is part of both the bias and gain setting which creates some compromises in setting the operating current. In your case the device (J310) has: VGS(off) of -2 to -6.5 V.
Zero volt VGS(ID) of 24 to 60 mA. (this is usually called IDSS, the zero VGS saturation current)
Note: This device is really designed as an RF amplifier where Rs would be zero.

Let's work through the design and see where the problems are when using a J310.
Ignoring Rd for the moment (assume it is shorted out while we bias the device operating current) if you look at Figure 1 in the datasheet, you can see the VGS curve (RHS of graph) for the device.

If VGS(off) is -2.0 V (the best of the J310 devices) the voltage across Rs can set the operating point (ID) somewhere under 2.0 V measured on the Source pin. Here is the Figure 1 with our extra information added: enter image description here Notice that with a 1K Ohm Rs the Source voltage will be about 1.8 V and the operating current about 2 mA. If we now tried to add back the RD value of 10K Ohm we have a real problem....to draw 2mA through 10k you need 20 V across it!!! The end result is that the JFET simply saturates, so you get no signal out. You should be able to confirm this by measuring VD and VS.

We'd typically expect that the quiescent point of VD (the Drain) should be about 2/3 of the supply voltage....or about3.3 V in this case. That means the value of RD would be about 750 Ohms. That would limit the gain to less than 1.
We just made an active attenuator...not very useful.

Let's select a device that might be more appropriate. We can try a J113: https://www.fairchildsemi.com/datasheets/J1/J111.pdf
This is a relatively common small signal JFET. There is still a range of VGS(off) and IDSS and the graphs are a little less helpful this time, but we can use Figure 6 and get an idea of where the operating point might be. If we use the VGS(off) value as -1.1 V there is a graph for it (but all the devices will vary of course).

enter image description here
We now have an ID of about 520 uA and a VS of about 520 mV. At this current the voltage drop across a 10k load resistor would be about 5.2 V ....closer to working, but it still won't work.

We have some choices to make if we want to keep the 1K in the Source side. We could drop the value of RD to set the voltage on the Drain to about 3.3 V, that would require RD=(5-3.3)/0.00052 --> approximately 3.3K Ohms. However this would limit our gain to 3.3.

Or we could get creative and make RS up of two resistors that total 1K Ohm and bypass one to ac signals.
To get a gain of 10 we need a 3.3K and 330 OHM RD and RS, leaving us 680 Ohms to be bypassed. The circuit would then look this way:


simulate this circuit – Schematic created using CircuitLab

  • \$\begingroup\$ Thanks for the detailed explanation. This is very helpful 😀 \$\endgroup\$
    – Alex K
    Dec 6, 2016 at 17:13
  • \$\begingroup\$ I got a gain of 6.3 for this circuit in LTspice. The gain is closer to R1/(R2+1/gm), and 1/gm is about 180 Ohms for J113. There is also a term in the gain equation to account for the output conductance. This reduces gain a little more. To get the gain of 10, R2=147 Ohms and R3=825 Ohms looks close, at least in LTspice. I used the J113 FET model at ltwiki.org/?title=Standard.jft . \$\endgroup\$ Dec 6, 2016 at 18:46
  • \$\begingroup\$ The formula for gain is of course a simplification, but in general gm can be ignored. I'd bet your LTspice ignores the effect of Rd//Rl for example. This a fair treatise of the simplifications: whites.sdsmt.edu/classes/ee320/notes/320Lecture32.pdf ... you are correct the gain will only be approximately R1/R2 but I don't think the OP was looking for the full theoretical derivation of gain. He was simply trying to get some gain instead of none. \$\endgroup\$ Dec 6, 2016 at 19:15
  • \$\begingroup\$ Excellent link, thanks! You are correct that the load impedance is another term to consider. Assuming the device being powered is a high impedance audio amp, input impedance is typically 150k to 1M music.stackexchange.com/questions/3473/… . The error in low-frequency gain due to the load is then 0.03db to 0.18dB. An even larger error is the unit-to-unit variation in the gm of the JFET, and possibly resistor tolerances. \$\endgroup\$ Dec 8, 2016 at 18:33

The gain of this circuit isn't set by the ratio of R2 to R1. The capacitor CS is shorting out R1, and helps with the gain. However, to do this at audio frequencies, the capacitor value needs to be much larger.

This circuit is an excellent example for learning LTspice. I suggest trying it, and you can get help from the LTspice mailing list if you need it. To get help from them, you will need to correctly upload an LTspice schematic showing what you tried.

The job of R1 is to set the drain-to-source current. The gate voltage will be about 0V. When the supply is turned on, the JFET will start to conduct, and the source voltage will rise because of the current in R1. It will rise until the JFET begins to turn off. This provides a little bit of negative feedback, and it will find an equilbrium point. This equilibrium point is set by the value of R1, and it should be adjusted until you have about 10mA, which is 0.75V across the 75 Ohm R1.

The resistor R2 can't be so large that the voltage on the source of J1 is too close to the voltage on the drain of J1. This is your analog output, and there needs to be a range of output where the drain voltage can vary without becoming equal to or less than the source voltage. That is the problem with the existing design.

This topic is called 'how to bias a transistor' and it is lots of fun. Search for "how to bias a JFET"

I tried the same circuit in LTspice, except I used a U309 JFET and a 9V supply instead of a J310 and a 5V supply. For my transistor, the values R2=750, R1=75, and C1=100uF gave reasonable results. The values that work will depend on the parameters of the transistor, and I don't expect them to work with the J310. Usually, IDSS and VGS(off) are enough to do the bias calculations, and these values are in the datasheet.

  • \$\begingroup\$ It's all starting to make sense now. When you say the job of R1 is to set Ids, it is doing that by setting Vds? I will try all this tomorrow, thanks for the great advice. \$\endgroup\$
    – Alex K
    Dec 6, 2016 at 5:56
  • \$\begingroup\$ The gain is set by RD/RS...it's just the values don't allow the device to be biased to work. \$\endgroup\$ Dec 6, 2016 at 7:49
  • \$\begingroup\$ There is another term to add to RS, which is 1/gm of the FET, which is about 180 Ohms for the J113. \$\endgroup\$ Dec 6, 2016 at 18:34

I made the circuit designed by Jack Creasey with some modifications for my needs:

  • I placed a 5K adjustable resistor for R1
  • I removed C2
  • I removed R4

Here are the FRA of 2 different boards:

enter image description here enter image description here

I hope I was helpful to someone.

Thanks Jack Creasey!


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