5
\$\begingroup\$

In the following example, a single clock is driving two loads. The traces to the loads have different lengths (10mm and 30mm). It is not feasible to make the individual routing lengths equal.

Clock specification: Frequency: 25Mhz, Output: HCMOS, Current: +/-24mA, Load: 15pF, Rise/Fall Time: 3ns

What would be the best approach for the clock termination in this case?

option 1. series termination

schematic

simulate this circuit – Schematic created using CircuitLab

option 2. parallel termination

schematic

simulate this circuit

\$\endgroup\$
  • \$\begingroup\$ What is the clock frequency? \$\endgroup\$ – Majenko Dec 6 '16 at 23:12
  • \$\begingroup\$ What is the rise and fall time of the logic family you are using? Termination is only needed when the round trip travel time is long with respect to the rise or fall time. For 30mm, in my head, the round trip is 200 ps. if your rise and fall times are 1 ns no termination is needed. \$\endgroup\$ – owg60 Dec 7 '16 at 0:25
  • \$\begingroup\$ @owg60 The Rise/Fall Time is 3 ns. \$\endgroup\$ – sergej Dec 7 '16 at 0:46
  • \$\begingroup\$ @sergej, be careful, CMOS parts normally spec rise/fall time with some specific capacitive load. Change the load, change the rise/fall time. \$\endgroup\$ – The Photon Dec 7 '16 at 1:57
4
\$\begingroup\$

The best way is to run one long trace and locate each of the loads as close to the trace as possible:

schematic

simulate this circuit – Schematic created using CircuitLab

Keep the stubs to the intermediate loads as short as possible.

HCMOS isn't really designed for resistive termination, so you could even possibly leave the termination off altogether. In that case it might be helpful to add a series resistance to the driver to limit the signal rise and fall times.

If you do need far end termination, then for HCMOS you'll prefer a split termination like I've shown. It would be even better to design the trace for higher characteristic impedance (85 or 100 ohms are common choices) and increase the termination resistance to match.

You do not want to use matched source series termination for this case, because this method relies on the reflected wave to bring the voltage on the line to the full logic level. This means that the intermediate loads along the line will potentially see an initial edge transition about halfway up or down, then "the rest of the edge" appear a few nanoseconds later. This can cause some dramatic jitter when the first part of the edge gets to an indeterminate logic level.

10 ohms or so in series with the driver output, though, may be helpful for reducing edge rate, and thus reducing high harmonic content in the signal.

\$\endgroup\$
  • \$\begingroup\$ Thanks for your answer. What would you propose if changing the trace routing is not an option (we can only add resistors at the driver or the loads)? \$\endgroup\$ – sergej Dec 7 '16 at 9:02
  • \$\begingroup\$ @sergej, I'd put a series resistor at the clock source's output, value TBD. These trace lengths are only just on the edge of being long enough to need termination. If you reduce the harmonic content by slowing the edges from the source, you should be okay. But this solution is not as good as one that reduces the stub lengths. \$\endgroup\$ – The Photon Dec 7 '16 at 17:57
  • 2
    \$\begingroup\$ Okay, sorry, I was reading 10 cm and 30 cm trace lengths. With 10 mm and 30 mm, it's very unlikely you need to worry about termination at all. I'd still probably put a 0-ohm series resistor at the source to give you a chance to adjust if needed, but very likely you won't need to change it. \$\endgroup\$ – The Photon Dec 7 '16 at 18:02
1
\$\begingroup\$

Given your problem you don't need to terminate the shortest trace of 10mm. The 30mm is probably too short to matter either. If you are concerned and laying out a PCB, put a spot for a Thevenin termination at the end of the longer run. Do not use a series termination for a situation like this. The half voltage reflections can potentially cause problems. Series termination is only good for single source to single load situations. The Thevenin termination is good because it doesn't create a large a load on the high side of the output gate like the parallel termination you are proposing. All of this also depends on what the characteristic impedance your traces have.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.