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I am using two STM8 micro-controllers as SPI masters. Master-1 is configured in full duplex mode. And the Master-2 is configured in Receive-only mode. The CS, MISO, MOSI and SCLK lines of Master-1 are connected to the Slave. The CS, MISO and SCLK lines of Master-2 are connected to the Slave. When Master-1 requests data from the slave. Master-1 and Master-2 should receive the data from slave at the same time. And the data should be same. I configured two masters with same baudrate,CPOL and CPHA.

When I am communicating with single master, I could receive the data correctly from the slave. But When I involve the second master in the communication the received data of both master is corrupted. And in the oscilloscope, I could see the SCLK variations on the slave.

What are the things I need to consider while communicating a slave with two masters at the same time.

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    \$\begingroup\$ The SPI master is the device that drives the SCLK line. You can't have two devices driving the same SCLK line at the same time. As simple as that. I think you have to take a step back and rethink your architecture. Or tell us the bigger picture of what you're trying to do, so we can give advice on that too. \$\endgroup\$
    – dim
    Dec 7, 2016 at 11:16
  • \$\begingroup\$ I am trying to get the data from the slave to two masters at the same time, but only one master should request the slave. When Slave responds to the request two masters should be able to read the data. \$\endgroup\$
    – GShaik
    Dec 7, 2016 at 11:21
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    \$\begingroup\$ Then, Master-2 shouldn't be a master. It's not initiating the communication, and it shouldn't drive SCLK. It could simply be another slave on the same bus (maybe with a few tricks if it needs to spy both MISO and MOSI). \$\endgroup\$
    – dim
    Dec 7, 2016 at 11:34
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    \$\begingroup\$ Why can't you just configure the 2nd master as a slave thus there will be no clock fights. \$\endgroup\$
    – Andy aka
    Dec 7, 2016 at 11:35
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    \$\begingroup\$ @AbdulGafoor If your system needs flow control to limit data rate slave-2 may be trying to control flow rate but not be able. What happens if you slow data rate for test purposes? Does error rate drop as data rate drops? Is there a rate at which you get no errors? What % of time is the SPI interface handling data actively. eg if << 50% of the time you could use two sessions. Either M->Sa, M-> S2 , or M->S1, S2 as M to S2. \$\endgroup\$
    – Russell McMahon ♦
    Jan 23, 2017 at 10:45

1 Answer 1

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As others have already said in the comments to your question - you can't simultaneously have 2 masters on an SPI bus. It just doesn't work that way.
But the setup you describe (ignoring your master/slave terminology) could work.
Only your Master-1 stays being a master. Your existing Slave stays as a slave, and your Master-2 becomes a slave, but you connect its data lines as if it's a master.
So:

schematic

simulate this circuit – Schematic created using CircuitLab

Your Master-1 will Chip-Select both Slave-1 & New-Slave-2(Old-Master-2) at the same time, and then when Slave-1 sends data out on its MISO, this data will be received by Master-1 on its MISO (as expected), and also by New-Slave-2 on its MOSI.

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  • \$\begingroup\$ As you suggested, I redesigned the architecture. Now Master-1 and Now Slave-2(Old Master-1) are receiving data frames from Slave-1. But in Slave-2 sometimes frames are missing. It is not receiving as expected, this scenario is occurring when I am accessing other peripherals like UART. I could see BUSY flag and OVERRUN ERROR in Slave-2's SPI. What could be the reason? \$\endgroup\$
    – GShaik
    Jan 23, 2017 at 9:59
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    \$\begingroup\$ You should be servicing the SPI in Slave-2 sing interrupts so make sure you read data coming in before the next byte arrives (which would cause an overflow). If you're already using interrupts for SPI, make sure that you have the interrupt priority set high enough that it 'interrupts' UART servicing. \$\endgroup\$
    – brhans
    Jan 23, 2017 at 12:53

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