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I am studying Computer Science and I am very confused. Let us say our Q is 1 and our Q* (Negation of Q) is 0. So when we go for R = 1 and S = 0, why isn't the value of Q* = 0?

I mean the NOR Gate for Q gives us Q = 0, which makes sense for me. But why is this value taken for the input of the NOR Gate for Q* instead of the earlier saved one (which was our 1). How is it accomplished? Shouldn't be the NOR Gate for Q as fast as the NOR Gate for Q*?

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  • \$\begingroup\$ Edit your question and provide a diagram either a picture or draw with the circuit diagram tool, without a better description this question is not answerable. \$\endgroup\$ – Voltage Spike Dec 7 '16 at 19:25
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So when we go for R = 1 and S = 0, why isn't the value of Q* = 0? I just don't get it.

enter image description here

When R = 1, it forces Q to be 0 (iirespective of nQ) and that puts a zero as an input on the other NOR gate. With S being zero on the other NOR gate input, nQ has to be 1. That's how it works.

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  • \$\begingroup\$ Sorry I meant Q* = 0. I edited it now. \$\endgroup\$ – J.Doe Dec 7 '16 at 18:43
  • \$\begingroup\$ Do'h do'h do'h! \$\endgroup\$ – Andy aka Dec 7 '16 at 18:43
  • \$\begingroup\$ Yea but I don't understand why the NOR Gatter at the bottom takes the 0 over the 1, since both gatters should be the same in speed. I assume they both put out their results in the same time, so why should the bottom gatter wait until the first one returns 0? \$\endgroup\$ – J.Doe Dec 7 '16 at 18:49
  • \$\begingroup\$ The gates output might change whenever its input changes. If Q changes, then the bottom NOR gate gets a new input, so its output might change. If Q* changes, then the top NOR gate gets a new input so its output might change. The gates don't know which wires are inputs to the whole gate and which are outputs. They just know which are inputs to themselves. \$\endgroup\$ – The Photon Dec 7 '16 at 18:52
  • \$\begingroup\$ @J.Doe: Both things happen, one after the other. Assuming that the R and S signals are held for some decent length of time, the nQ signal will become 1 early on and then hold as long as R and S remain stable. Circuit nodes don't have single values, they vary over time. And glitches do happen (such as Q and nQ both being 1) but they don't last long. \$\endgroup\$ – Ben Voigt Dec 7 '16 at 18:52
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I believe you are talking about an RS latch when you say Flip Flop.

Lets considder this RS-latch:

¬(R V ¬Q) = Q

¬(S V Q) = ¬Q

As there are two inputs and two states per input we have a total of 2^2 = 4 possible states:


  1. S = 0, R = 1

¬(R V ¬Q) = ¬(1 V ¬Q) = ¬(1) = 0 = Q

¬(S V Q) = ¬(0 V Q) = (¬Q) = ¬Q, Q = 0 => ¬Q = 1

Result: Q = 0, ¬Q = 1 => Q has been RESET


  1. S = 1, R = 0

¬(S V Q) = ¬(1 V Q) = ¬(1) = 0 = ¬Q

¬(R V ¬Q) = ¬(0 V ¬Q) = ¬(¬Q) = Q, ¬Q = 0, ¬(¬Q) = ¬(0) = 1

Result: Q = 1, ¬Q = 0 => Q has been SET


  1. S = R = 0

¬(R V ¬Q) = ¬(0 V ¬Q) = ¬(¬Q) = Q

¬(S V Q) = ¬(0 V Q) = ¬Q

Result: Q = Q, ¬Q = ¬Q => Q remains UNCHANGED


  1. S = R = 1

¬(R V ¬Q) = ¬(1) = 0 = Q

¬(S V Q) = ¬(1 V Q) = ¬(1) = 0 = ¬Q

Result: Q = 0, ¬Q = 0, this state is useless/FORBIDDEN


I hope this helps...

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