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I am trying to figure something apparently basic and I hope somebody might give me an advice. The IC I am working with is XC6SLX25. It has 6 different power regions -- Vccint, Vccaux and Vcc for each of the four banks. Xilinx provides a PCB design guide (UG393) where they specify the number and type of decoupling capacitors per each power region but still I am not sure how to connect them to all the pins.

For example the guide states that one 100 uF, one 4.7 uF and two 0.47uF capacitors should be connected to the power pins of Bank 1. Vcco1 pins highlighted GND pins highlighted According to this guide 100 uF capacitor could be placed almost anywhere near the IC, 4.7 uF should be placed within 2 inches of the outer edge and 0.47 uF should be preferably placed on PCB backside. As it can be seen on the attached pictures there are 6 power pins and 6 GND pins located on Bank 1. My questing is this -- what is the correct way to connect these four capacitors to the six pairs of pins? Should each type of a capacitor be connected to each pair of pins and if so how should the capacitors be interconnected?

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All the ground balls go down to the ground plane by means of local vias, and all the power pins on any given rail go down to a power plane region on the appropriate rail, then you place the caps as per the note and connect them to the appropriate places.

Probably the small caps go on the back under the appropriate power plane region and just via thru to the plane and ground (Two vias per cap terminal are better then one when you can fit them).

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  • \$\begingroup\$ I still don't quite understand how I should distribute 4 caps between 6 pin pairs. It seems natural that each pin must be connected to each type of a capacitor. Which means that on Bank 1 there should be 3 Vcc pins connected to each 0.47uf cqp, 6 pins connected to 4.7uF and 6 pins connected to 100uF, but I have trouble imagining such a connection. \$\endgroup\$
    – Lee Brown
    Dec 8, 2016 at 14:09
  • \$\begingroup\$ What is your stackup? 4 layers? 6 layers? 8 layers? I am assuming you have a solid ground plane under the part, probably on layer 2, which all the ground balls can just be tied down to with vias. You then pour a polygon under the IO bank, probably on layer 3 or so, which you connect to the power pins with more vias, the small caps then go on the back of the board and connect between the ground plane and the power polygon with vias as close to the chip as possible. If desired the power polygon can extend out to pick up the 4.7uF caps as well, it doesn't hurt if you have the space. \$\endgroup\$
    – Dan Mills
    Dec 8, 2016 at 14:16
  • \$\begingroup\$ My stackup is 4 layers with power plane and ground plane in the centre. If I understand you correctly, caps should not be connected directly to power pins, instead they are all attached to a polygon under the IO bank? \$\endgroup\$
    – Lee Brown
    Dec 8, 2016 at 14:25
  • \$\begingroup\$ That is what I usually do yes. The polygon is going to have a lower inductance then anything else you could do, and you can sometimes use the bottom end of the via that connects to one of the pins for one side of a cap, doesn't hurt anything. \$\endgroup\$
    – Dan Mills
    Dec 8, 2016 at 14:35
  • \$\begingroup\$ You don't always get the ideal thing, especially when working on 4 layers with a BGA to fan out, but power polygons are a happymaking thing, especially as the voltages get low and the currents large. \$\endgroup\$
    – Dan Mills
    Dec 8, 2016 at 14:40

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