# Why is there a non-zero phase error in a second-order PLL?

Why is there a non-zero phase error in a second order PLL even though there is an integrator in the loop (type-1 system)? The same transfer function is applicable whether frequency or phase is considered as the input. Why then, under locked condition,steady state error for a step-change in frequency is zero but is non-zero for phase?

• The same reason controlling speed with a tachometer and control loop containing an integrator does not guarantee displacement. You're not integrating the phase difference. Commented Dec 9, 2016 at 16:57
• A type I phase comparator always produces a 90 degree phase displacement (when locked) so are you talking about that or a phase error in addition to the 90 degrees? Commented Dec 11, 2016 at 15:49
• @Andyaka I don't understand what you mean when you say that in locked condition phase error is always 90 degrees. As I understand, in locked state, reference frequency and output frequency are same, and phase error depends on the input frequency. As input frequency changes, the VCO control voltage shifts so that output can track the input. The new phase error now corresponds to the changed VCO control voltage. Commented Dec 15, 2016 at 15:25
• Then you need to look at how a type 1 phase comparator works. That's the whole basis of the answer I gave. Commented Dec 15, 2016 at 15:29
• Is my understanding wrong? Commented Dec 15, 2016 at 15:31

A frequency step is identical with a ramping phase (phase is the time integral over frequency). Therefore, speaking about phase errror (for a frequency step) we do NOT speak about a "static" but about the "dynamic" error (or phase "tracking" error).

Applying the "Final Value Theorem", we find that (a) for a simple lag-filter we have a finite (tracking) phase error, but for a PI filter the dynamic phase error is zero.

Explanation (Loop gain): LG(s)=H(PI)*H(VCO)=K1(1+1/sT1)*K2/s.

Because of Delta(phi)=Delta(w)/s the "s" in the denominator of LG(s) cancels and the "Final Value Theorem" for the phase-transfer function (with s=0) gives a finite (correction: infinite !)value for the loop gain LG in case of a PI controller).

Why is there a non-zero phase error in a second order PLL even though there is an integrator in the loop (type-1 system)?

That non-zero phase error is 90 degrees.

A type I phase detector is at "equilibrium" when the phase angle of the unknown and reference frequencies are displaced by 90 degrees. In other words, when in lock, the output error signal is zero (or at balance) and hence the integrator cannot do any more work and the two frequencies are in-lock but 90 degrees apart.

A typical type I detector is an exclusive or gate like this: -

You should be able to see from the graph that the natural balanced condition is when the phase angle difference is pi/2 or 90 degrees. This produces an output from the XOR that has a 50% duty cycle i.e. the mid-point.

• When you say equilibrium, do you mean lock? Wouldn't the loop be in lock while PD is operating on any point (between 0 to Pi) and not just 90 degrees? Commented Dec 16, 2016 at 5:14
• When I talk about the phase detector on its own I use terms like equilibrium and balance but I use the term lock to refer to the whole PLL. If you have an integrator in the loop (as per your question) then no, the pll will always lock at 90. Don't ask me to explain why other answers don't mention this. Commented Dec 16, 2016 at 8:21