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schematic

simulate this circuit – Schematic created using CircuitLab

I am trying to design an overvoltage protection circuit. And this is the circuit above, and this is the LtSpice circuit below: enter image description here

This circuit somehow manages to function correctly. Meaning, it accepts input only for voltage level between 2V -3.6V, when higher voltage is applied, it closes the PMOS (M4 in CircuitLab and M1 in LtSpice).

But the problem is ripple and the spikes! I know spike is formed because M1 can not open fast enough to compansate fast rise of Vin to gate of M2. But I can't think anything for getting rid of ripples.

lt clab

spike occurs at both circuitlab and ltSpice.

enter image description here

But in circuit lab, ripples not seen.

Thanks in advance.

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    \$\begingroup\$ Well, I'm darned if i can figure out what your circuit does. \$\endgroup\$ – Andy aka Dec 9 '16 at 19:39
  • \$\begingroup\$ @Andyaka Basically, this circuit's usecase is something like this: Think that you have a circuit and If you supply this circuit with more than 5V it burns out. So you want to protect it for mis cable placement. If you use this circuit as a pre input stage to the circuit, it won't allow more than 3.6V to the input. So Vout here is the Supply input for the real circuit. I hope I explained it well. \$\endgroup\$ – Alper91 Dec 9 '16 at 19:46
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    \$\begingroup\$ What's wrong with Zener Diodes? That's the traditional way of dealing with transient spikes. Zeners for spike supression are typically called MOVs (a brick of thousands of tiny zeners mashed together) or Transorbs (back to back zeners) or what Horter suggested, add a filter... or both \$\endgroup\$ – Sam Dec 9 '16 at 22:50
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The most basic way to get rid of voltage spikes is to low pass filter them. Make C1/C2 (1uF) bigger and see what your results are.

The other way is to make M1 shut off faster of course. To pinch it off faster, you would have to lower R6 so that the voltage spike travelling down the line transfers its energy to the Gate of M1 faster. R6 is the path to do that.

Something that makes me wary of the circuit is the position of L2. It's most likely being used as part of a low-pass filter to begin with, but in the event of a voltage spike, the position of M1 with the inductor causes a significant voltage spike on the left side of M1 as M1 is shutting off. This could exacerbate the problem you're seeing. To get around this, you may want to add a diode across L2 facing backwards to allow any inductive spikes you cause to bleed out through the diode. Look up voltage-snubbers for more info on this.

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There are a few things I don't understand in your circuit, but mainly the presence of the inductor, which seems small enough to not matter for the seconds worth of switching signals, but also significant enough to give a nice, short kickback, to matter as a spike.

While your circuit seems small enough (which might suggest a need for simplicity), may I suggest an alternative, maybe with 339 or similar open-collector:

schematic

Q1 and Q2 are the internal open-collector, and Q3 is there for inversion. The thresholds can be easily calculated, I'll leave that to you, if you want this. It's a simple schematic, meant to show you the alternative, not to present you with a full schematic.

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Solved.

I added shunt capacitor between M1's gate and source.

enter image description here

So this way VSG voltage of M1 increases faster than before also, when M3 also triggered, \$\frac{C_1 // R_6}{C_{SG} // R_{DS3} + C_1 // R_6}\$ stays small since \$C_1\$ is much more bigger than \$C_{SG}\$ so M1 remains closed.

enter image description here enter image description here

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    \$\begingroup\$ ...you took out an inductor... \$\endgroup\$ – horta Dec 9 '16 at 22:30
  • \$\begingroup\$ @horta yes first I took out the inductor and thank you for that suggestion :) I gave an upvote but it didn't remove spike or ripples. Bypassing Vsg did though. \$\endgroup\$ – Alper91 Dec 10 '16 at 9:54
  • \$\begingroup\$ Gotcha. Glad you got it fixed! \$\endgroup\$ – horta Dec 10 '16 at 17:02

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