# Output of Sample and Hold Circuit

I'm having a bit of a problem figuring out how this sample and hold circuit works.

I am to calculate $V_\text{out}$ if (a) $A$ is infinite and if (b) $A$ is finite. $A$ is the open-loop gain of the OpAmp, and $V_\text{DAC}$ is a DC voltage.

What is $V_\text{out}$ in the two cases (a) and (b)? • I thought it was rather implicit in the way I wrote it. But now an actual question has been added. Dec 9, 2016 at 22:14

In Phi1 CF is connected to ground on both sides and gets discharged. Cs is charged to Vin.

In Phi2 the OpAmp is in a feedback configuration. The difference of the voltage VDAC-Vin appears at the negative terminal of the opamp. For a positive voltage, in the first instant the output of the opamp will swing in the negative direction. Cs gets charged and the differential input voltage across the - and + terminals becomes smaller and smaller.

For infinite gain the difference between the + and - inputs of the opamp will become zero, the voltage VDAC will be stored onto CS, CF will hold a scaled version of VDAC-Vin it, depending on the ratio of Cs/Cf.

For finite gain a small voltage will remain across the input of the opamp. Again a scaled version of VDAC-Vin will be seen across Cf.

Happy calculations!

• Isn't Cs in Phi1 charged with Vin? Dec 9, 2016 at 21:56
• Sorry, didn't see that. Doesn't change much. I'll edit the answer. Dec 9, 2016 at 22:00
• Thank you. Why is it that the infinite gain will result in an output of zero? Dec 9, 2016 at 22:06
• The difference between + and - will become zero. For a finite gain it will be Vout/Gain. Dec 9, 2016 at 22:07
• Can you give an explicit calculation example of finding Vout? Dec 10, 2016 at 0:44

When ϕ1 closes both -in and out are grounded discharging Cf and charging Cs from Vin. Then ϕ2 closes the feedback loop so successive approx registers from DAC computes the Vin by nulling Vout.

This is part of a SAR ADC.

Loop gain affects gain error of Cf/Cs just like R ratios at high frequency, which limits DAC speed.