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Consider a CDMA transmitter using DSSS that is in motion with respect to the receiver (satellite). Suppose the PN code is synchronized to within one chip, i.e. acquisition has been completed. How is code tracking implemented currently on FPGAs?

What I'd like to do is to use a PLL in order to synchronize to the satellite chip clock. The theory is to maximize cross correlation by steering the PLL. However, it seems that I am not able to modify the phase detector inside the PLL in the FPGAs on the Altera parts.

What I can think of is:

  1. Use external PLL
  2. Use an all digital PLL with an NCO (has a finite phase shift error)
  3. Find an FPGA that has internal PLLs with the ability to use a custom PD
  4. Implement an internal PLL out of the FPGA logic, and have an external VCO and filter
  5. Have a control loop that modifies the PLL counters

So, what is generally used for such a system nowadays? Any app notes on the subject?

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  • \$\begingroup\$ Just to be sure, you want to despread in the analog domain, before sampling? In the digital domain it would be complicated, because your (steered) code-generation clock is asynchronous to the sampling rate. I cannot tell what is generally used, by I use an NCO and despread in digital domain. If you carefully choose the sampling rate to avoid beating, you can zero residual error. \$\endgroup\$ – Andreas Dec 10 '16 at 17:54
  • \$\begingroup\$ @Andreas No, I want to despread in the digital domain. I want to generate a clock that has the same rate as the chipping clock at the receiver + the Doppler shift. So I can have a shift register feeding the PN code. I hadn't thought about the sampling rate. I can see how that can be a problem. \$\endgroup\$ – user110971 Dec 10 '16 at 18:01
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Different clocks and rates need to be considered:

  1. The (received) chip-rate of the signal (altered by doppler)
  2. The sampling rate
  3. The clock(s) your FPGA is running on.

signal-synchronous designs

Your proposal using the internal PLL would require running part of the FPGA-logic (the code generator) with a fixed phase relation to the received chip-rate (which is variable for a moving receiver/transmitter). Since you want to modulate this code onto the received signal, the sampling process would also need to be fixed phase to the chips. Combining signals from different clock-domains in a mixer is impossible (unless you employ sample rate conversion, don't even think about this).

So basically everything is fixed to the chip-rate. I dare to say that this is not a common setup, since most systems have additional timing constraints, f.e. for memory interfaces, and GNSS receivers need to track more than one signal.

numerical controlled oscillators

To be independent from the varying observed chip-rate, you need to employ a numerical controlled oscillator. This oscillator can run on the sample-rate or the FPGA-clock. Running it on the sample-rate makes things easier since there is only one local clock error.

You may want to make sure, that the fraction between sample-rate and chip-rate is not a low-order harmonic. In fact, spurious tones cannot be avoided completely but consideration of quantization noise and its harmonics and the effect on your signal can save your day. Fractional-N is a must, dithering may help.

I daresay that this is a very common setup.

optional: FPGA-clock >> sample-rate

You may be tempted to run the FPGA-logic on the ADC-clock. This facilitates simple modules since there is valid data in every clock-cycle. However, this typically only works for a part of your design. If you have a decimating filter, your symbol rate will be lower after that filter and asynchronous signaling (Avalon ST) is mandatory.

Using asynchronous design (with logic clock > sample rate) from the very start of you signal path gives you additional value:

  1. You can time-multiplex some of your signal-path.
  2. You can stop or reconfigure the ADC without putting the FPGA on hold.
  3. Implicit dependency on clock is a avoided for your HDL, making it easier to understand.
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