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hi first of all english is not my languaje. im using a SPARTAN 3E as develop board i tried to make a FSM that changes the state with a counter called "T" (somethig like a pseudo-processor) and use a button as pulse to increment, in one case the FSM asign a 4 size std_logic_vector from four switches in the fpga board to "A", then increment the counter and in other time put the value from the same switch in "B", finally it makes the operation C:=A+B and send it to two external displays the main problem happens when i want to make the adition between A and B, looklike A and B doesnt hold the asigned value and shows a wrong operation when i tested, im new in vhdl so my knowledge is limited thanks for the help :)

  `PROCESS(T)

   variable A:    std_logic_vector(3 DOWNTO 0);
   variable B:    std_logic_vector(3 DOWNTO 0);
   variable C:    STD_LOGIC_VECTOR(4 DOWNTO 0);
   BEGIN 
    IF T="00000" THEN--0
       X0<="00000011";  
    END IF;

    IF T="00001" THEN--1
        IF MEM="0001" THEN 
           VAL<="00001";
        ELSE
           VAL<="11111";
        END IF;
        X0<="00000110";
    END IF;

    IF T="00010" THEN--2
      X0<="00011010";
    END IF;

    IF T="00011" THEN--3
      X0<="00000011";
    END IF;

    IF T="00100" THEN--4
       VAL<=('0'& MEM);
       X0<="00000110";
    END IF;

    IF T="00101" THEN--5
        A:=MEM;--takes A from the switch 
        VAL<=('0' & A);
        X0<="00110010";
    END IF;

    IF T="00110" THEN--6

       X0<="00000011";
    END IF;

    IF T="00111" THEN--7
        B:=MEM;--takes B from the switch
        VAL<=('0' & B);
        X0<="00000110";
    END IF;

    IF T="01000" THEN--8
       X0<="01010010";
    END IF;

    IF T="01001" THEN--9
       C:=STD_LOGIC_VECTOR(UNSIGNED('0' & A)+UNSIGNED('0' & B));
       VAL<=(C);--shows the result 
       X0<="10000010";
    END IF;

    IF T="01010" THEN--10
        X0<="00000011";
    END IF;

    IF T="01011" THEN--11
        IF MEM="0001" THEN 
           VAL<="00010";
        ELSE
           VAL<="11111";
        END IF;
        X0<="00000110";
    END IF;

    IF T="01100" THEN--12
        X0<="00011010";
    END IF;

    IF T="01101" THEN--13
        X0<="00000011";
    END IF;

    IF T="01110" THEN--14
        VAL<=('0' & MEM);
        X0<="00000110";
    END IF;

    IF T="01111" THEN--15
        A:=MEM;--takes A 
        VAL<=('0' & MEM);
        X0<="00110010";
    END IF;

    IF T="10000" THEN--16
        X0<="00000011";
    END IF;

    IF T="10001" THEN--17
        VAL<=('0' & MEM);
        X0<="00000110";
    END IF;

    IF T="10010" THEN--18
        B:=MEM;--takes B
        VAL<=('0' & B);
        X0<="01010010";
    END IF;

    IF T="10011" THEN--19
       C:=STD_LOGIC_VECTOR(UNSIGNED('0' & A)-UNSIGNED('0' & B));
       VAL<=(C);--shows the result
       X0<="00000000";
    END IF;

    if T>"10011" then
       X0<="00000000";
    end if;

END PROCESS;`
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  • 6
    \$\begingroup\$ Your best approach is to learn about synchronous (clocked) processes. \$\endgroup\$ – Brian Drummond Dec 10 '16 at 20:47
  • 2
    \$\begingroup\$ Does it work in simulation? \$\endgroup\$ – Martin Thompson Dec 12 '16 at 15:14
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This might not work out so well depending on your synthesis tool. All your signals and variables will be implemented as latches, which is in any case not a good idea.

I assume that T is generated in a synchronous process with a clock. If you convert your asynchronous process to a clocked process as well that will probably solve your problems. E.g.:

PROCESS(clk)
variable A:    std_logic_vector(3 DOWNTO 0);
variable B:    std_logic_vector(3 DOWNTO 0);
variable C:    STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN 
  IF rising_edge(clk) THEN
    IF T="00000" THEN--0
(...)
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