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4Gbps PAM4 signal
I've been recently testing a self-designed PAM4 transmitter(TX).The transmitter is intended to work at a data rate of 40Gbps,and it really does work in the simulation tool(Cadence)under various PVT,so that I've gained much confindence.

However,I am totally a novice in the field of PCB design,(not to say the high-speed one)and I basically designed this circuit board with some guidelines over the Internet(lol,I promise I read a lot).

Now with some basic measurements conducted,the result is far from good enough:the eye diagram is almost closed at 28Gbps,so I slowed the TX a little bit,to the speed that I am fully confident about(@4Gbps).As can be seen in the pic,it still turns out to be working in a bad state:edges are not clear at all,levels are rough.

So if the IC itself is assumed to work as satifactorily as in the simulation tool(sharp edges and flat levels),what could possibly go wrong from a pcb perspective to cause problems in the pic?

enter image description here

SMA_CLK_BP&SMA_CLKB_BP are the ports which high-frequency clocks (provided by BERT) come in.SMA_TXP&SMA_TXN are the output ports for the PAM4 signals shown in the picture.

There are some bypass capacitors(SMT) and ferrite beads around,mostly on the bottom layer,to serve the supply.

For simplicity sake,some pull-up/down resistors have been omitted in the schematic.

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  • \$\begingroup\$ That's not too bad for 4 Gbps but I can see that at 28 it will be problematic. Without a schematic and PCB layout, it's guesswork but I can understand that you might want to keep IP safe. \$\endgroup\$
    – Andy aka
    Dec 12 '16 at 8:39
  • \$\begingroup\$ @Andy It's no about IP,but stackexchange's restrictions on uploading document.Since I have no idea where to start,could you provide me some guess,and maybe it will work. \$\endgroup\$
    – Xiao Xiang
    Dec 12 '16 at 9:06
  • \$\begingroup\$ If you can upload pictures to some share site then leave a link in this comment area I can edit your question to incorporate the pictures but try and be concise with information i.e. stick to the parts that are relevant. Best guess - reflections, mismatch, badly calculated track capacitance. \$\endgroup\$
    – Andy aka
    Dec 12 '16 at 9:17
  • \$\begingroup\$ @Andy I've updated the PCB layout above:) \$\endgroup\$
    – Xiao Xiang
    Dec 12 '16 at 11:14
  • \$\begingroup\$ And the schematic? \$\endgroup\$
    – Andy aka
    Dec 12 '16 at 11:15
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The SMA connector grounding looks like a problem to me. There are traces going to vias, which I assume connect to a ground plane. Instead, I think there should be something like 20 vias in each pad going to the ground plane. The via-in-pad process adds cost to the PC board, but I think in this case it is required. If you add some inductance to the connector ground pin in a simulation model, you may see the problem.

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  • \$\begingroup\$ Actually I have already added like 10 vias going to the ground plane around the signal via,which is connected to the trace of TX output.By the way,do you think the traces could be a problem since they wind a lot when leaving the chip? \$\endgroup\$
    – Xiao Xiang
    Dec 13 '16 at 5:46
  • \$\begingroup\$ What is the substrate material? FR-4 would have a lot of loss. (Sorry, I can't give advice here on choosing substrate materials.) If you have access to ADS, it has a lot of functionality for simulating PC boards at microwave frequencies. The latest ADS patch adds more. (Full disclosure - I work on ADS-related projects, but here I am writing for myself and not Keysight Technologies). \$\endgroup\$ Dec 13 '16 at 6:20
  • \$\begingroup\$ We now choose Rogers 4350B as the substrate material. I will have a try at ADS,thanks. \$\endgroup\$
    – Xiao Xiang
    Dec 13 '16 at 11:34
  • \$\begingroup\$ I think you are correct that you should be able to improve your results with layout. I think ADS has sources for the eye pattern that you are using. The latest patch has more features for signal integrity called SIPro and power integrity tools called PIPro. \$\endgroup\$ Dec 13 '16 at 15:59
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Lots of jitter on the edges there, what is your clock source and is there an on chip PLL in play?

The top and bottom of the eye do not look horrible to me, some signs of impedance discontinuities but I would guess that a lot of that is the transitions to SMA cables, it is the edge timing that seems very poor to me.

Can you get a jitter histogram out of that instrument, and maybe also a phase noise plot?

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  • \$\begingroup\$ No,there isn't a on-chip PLL,for now TX works on clock provided by BERT.This BERT has produced pretty good examples on the other PAM4 TX for rate over 30Gbps,so I assume this is not a great concern,but I will definitely try to get its jitter.Could you give me more clues on the edge timing stuff? \$\endgroup\$
    – Xiao Xiang
    Dec 12 '16 at 11:37
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Judging from the balanced nature of the jitter, I think its from your IC, or your clocking setup, and NOT THE PCB.

One challenge with jitter is the need to perform system analysis, and not just assume FAST edges will be adequate. [Is your input clock of high amplitude with fast edges?]

If the internal nodes of a gate or amplifier are slow, and the output edges are fast (you burned more power to achieve that fast output), you'll have more jitter than if you burned power all the way along the signal chain.

Your jitter looks balanced, left to right about the vertical edges. That means its random, and not deterministic. Have you operated some gates or amplifiers or clocked-latch at low power, then used FAST output drivers?

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  • \$\begingroup\$ I still don't get the burn-power thing,it sounds plausible to produce more power to get a fast edge,but how should that be related to the jitter?In order to help the high-frequency clock(10GHz) to work,I adjust the buffer fanout to be 2:3,so that means adding lots of buffers to form a 10GHz clock chain(over 20x),will that possibly responsible for the jitter? \$\endgroup\$
    – Xiao Xiang
    Mar 11 '17 at 2:16

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