I've been recently testing a self-designed PAM4 transmitter(TX).The transmitter is intended to work at a data rate of 40Gbps,and it really does work in the simulation tool(Cadence)under various PVT,so that I've gained much confindence.
However,I am totally a novice in the field of PCB design,(not to say the high-speed one)and I basically designed this circuit board with some guidelines over the Internet(lol,I promise I read a lot).
Now with some basic measurements conducted,the result is far from good enough:the eye diagram is almost closed at 28Gbps,so I slowed the TX a little bit,to the speed that I am fully confident about(@4Gbps).As can be seen in the pic,it still turns out to be working in a bad state:edges are not clear at all,levels are rough.
So if the IC itself is assumed to work as satifactorily as in the simulation tool(sharp edges and flat levels),what could possibly go wrong from a pcb perspective to cause problems in the pic?
SMA_CLK_BP&SMA_CLKB_BP are the ports which high-frequency clocks (provided by BERT) come in.SMA_TXP&SMA_TXN are the output ports for the PAM4 signals shown in the picture.
There are some bypass capacitors(SMT) and ferrite beads around,mostly on the bottom layer,to serve the supply.
For simplicity sake，some pull-up/down resistors have been omitted in the schematic.