When implementing something build with flip-flops and logic gates, why do we aim to minimize the number of flip-flops even if it produces more gates? Does it have to do with minimizing the delay, the energy or something else? Could someone explain this?
Modern FPGAs do not contain "gates" as such; the logic is implemented by LUTs (lookup tables) or MUXes (multiplexers). As such, the number of "gates" is not really the limitation in terms of either resources or delay.
With a LUT, the only key parameter is the number of inputs required to produce a given output function; the function itself can be completely arbitrary. It could be the equivalent of a single gate or dozens of gates, with no change in the "cost" of using it.
Therefore, the synthesis software for FPGAs only needs to pay attention to the number of FFs used and the number of LUTs used. Usually, there is one of each in the lowest-level "logic cell" in the FPGA's hierarchy.
It boils down to efficient use of FPGA resources.
There aren't actually gates in a FPGA (in the usual sense of the term). There are, however, a lot of LUTs (Look-Up-Tables), multiplexers, adders, and flip-flops.
Here is a typical FPGA slice:
Now, you have to understand that, using very few LUTs, you can build rather complex combinatory logic. A single LUT can achieve the same result as a combination of multiple AND/OR/NOT gates.
On the other hand, a flip-flop is a flip-flop. There is no trick to lower the number of required elements, here.
So, usually, complexifying the combinatorial logic (the "gates") is not much of a problem (and, in some situations, it may not even lead to an increase of resources used). However, if you use more flip-flops, you will necessarily use more FPGA resources.
Also, the syntesis tools have much more ways to optimize combinatorial logic than optimizing the flip-flop usage. If you did your design right (e.g. there is no flip-flops that are duplicated or whose output isn't actually used), the tools can't do much to reduce flip-flop usage.