# Why setup time is greater than hold time?

One of my friend was asked this question in an interview. What should be the answer? One more question how hold time can be negative?

• It depends on what you are talking about. – Andy aka Dec 12 '16 at 22:52

Why setup time is greater than hold time?

Who says that it is? It depends very much on the design of a particular sequential circuit.

However, it is often desirable for setup time to be greater than hold time (or put another way, for hold time to be as low as possible), because this means that you can cascade FFs directly to create shift registers, etc. without having to worry about metastability.

How can hold time be negative?

You can trade off between setup and hold time by adding a delay in either the data input path or the clock input path. If the delay that you add to the data is greater than the FF's actual hold time requirement, the overall hold time requirement for the combination can be negative.

• It might be important to point out that while either setup or hold can be positive or negative, the expression "setup + hold > 0" must always be true (relative to the clock edge your setup time must occur before your hold time). – jbord39 Dec 13 '16 at 0:09
• @jbord39: Yes, that sum represents the width of the "metastable window" that is implicit in the design of the circuit in question. You can move it around using delays, but any uncertainty in the length of the delay can only add to the width of the window. – Dave Tweed Dec 13 '16 at 1:32
• @DaveTweed Setup time should also be as low as possible. Setup time can also create metastability. Am I right? If it is right than why not reducing setup time instead of hold time. – Nikhil Pandya Dec 13 '16 at 19:34

Why setup time is greater than hold time?

This is true in most cases and it mainly depends on the architecture of Flip Flop being used. Consider the master slave flip flop below:

The propagation delay of the darkened path (fig 1) is the setup time. When the clock goes high, the path WXYZ forms a loop propagating the data that was floating at Z at the moment and we have to make sure that D has gone all the way to Z before clock goes high. Hence the setup time constraint.

For hold time, the darkened path in the above picture (fig 2) is only considered. when the clock toggles high, it takes some delay for T1 to shut off and we have to make sure only the right value of D goes through to W. So, the value of D should remain constant for the period equivalent to the delay of T1 minus the delay of the inverter before T1.

Hold time could be NEGATIVE if the delay of the inverter is greater than the delay of T1.