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I'm working on a project and have been banging my head against the wall for the past couple of weeks with the DDR3 fanout and wiring. I'm trying to keep the cost to the minimum, so I'm using the most cost-effective DDR3 IC's I managed to find, which is 512Mb x16 96-ball packages by Kingston and have four of them connected to an ARM Cortex-A7 CPU. Since I've entirely rerouted the memory subsystem abt a dozen times, trying to fit everything on a 4 layer board with components only on one side (for cost and aesthetic reasons), I decided to check how many layers other people have used for similar projects? As far as I can tell by the laminate of some SBCs I have, others have used at least 6 layers for this. Some seem to go for single chip twin- or quad-die 32x options, but that stretches the production costs by a lot, and I'm trying to keep the costs down.

Has anyone succeeded in routing 2 channels with 2 x16 chips each on a 4-layer PCB, with proper length and skew tuning? I would go for 6-layer PCB, but the price jumps almost twice, and I'm already stretching my wallet with the 4mils(0.1mm) track width and 8mils(0.2mm) via holes. Going to 6 layers, the price hike is significant regardless of the track widths and min drill sizes used.

Any suggestions how to do this better and more efficiently?

Thanks in advance!

vlex

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  • \$\begingroup\$ We have been struggling to have the same thing. We are now good with 6 layer board. Intel atom processor + DDR3 from micron. All is well now. Good to go with 6 layer, in order to take advantage of DDR3 \$\endgroup\$ – Umar Dec 13 '16 at 5:43
  • \$\begingroup\$ What do you mean with "Good to go with 6 layer, in order to take advantage of DDR3"? \$\endgroup\$ – vlex Dec 13 '16 at 6:14
  • \$\begingroup\$ I meant - Our design was working with 6 layer board, with the DDR3 full speed. Hence, the matching was good and it was one time design effort. \$\endgroup\$ – Umar Dec 13 '16 at 6:50
  • \$\begingroup\$ @vlex if you have a board with components only on one side then how are you going to decouple 4 DDR3 chips and an A7 processor? All of the recommended layouts have the decoupling caps on the back of the board where they can be close to the power and ground pads. \$\endgroup\$ – Steve G Dec 13 '16 at 9:41
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Consumer's telecom router achieve to route DDR2 and DDR3 on 4 layers board.

I've worked on several routers, not on design phase, but vast majority of this high-volume products use PCB with only 4 layers. Using 6 layers prompt a lot of discussion about cost and you should demonstrate that you really can't do a board with 4 layers.

One example of this kind of product: 2 DDR2-400 x16 chips.

enter image description here

Another teardown from IHS but pictures are low quality, this box also feature 2 DDR2 chips on a 4 layers PCB: http://electronics360.globalspec.com/article/3410/netgear-super-hub-2-vmdg485-wireless-router-teardown

Are you taking advantage of bit and byte swapping that DDR3 offer ? It can really help layout by avoiding a lot of crossing.

About costs I'm suprised about Kingston, I never saw a product with their DDR chips. In telecom I mostly see Hynix, Nanya, Winbond and sometimes Etron(tech).

Also talking about 1k quantity prices means to me that you are buying through a distributor and not talking with the manufacturer. So taking the time to contact DRAM manufacturer to negociate price is not something to do at the end, because you may be able to have some easier-to-route DRAM chips at the same cost than a not-negociated DRAM.
You won't save on final BOM price, but you'll save on layout complexity/feasibility and maybe EMC.

Edit: you're talking about 2 x32 channels, if the controller's pinout is mixing the two channels you can't achieve this on a 4 layers PCB.
But if the two channel are more or less separated it may be possible, however you may have to sacrifice other signals to allow DDR signals to pass.

LPDDR3 can also help if controller support it.

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4 Layer is poor for EMI and 6 layer is marginal but possible on DDR3, while 8 layer is better than 6. More layers is always better performance for crosstalk and unintended EMI.

The price should be proportional to the total weight of copper in volume or the number of layers, so unless you Blind or Buried Vias (BBV), your assumptions on cost are incorrect. The cost of 8 layer vs 6 is not double. Use microvias and avoid BBV's, which are big cost drivers or find another shop.

www.ti.com/lit/an/scaa082/scaa082.pdf

also https://e2e.ti.com/support/arm/sitara_arm/f/791/t/407051

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  • \$\begingroup\$ It is not a mere assumption, it's a cross comparison of the prices for prototyping quantities (less than 30pcs) on as many as possible PCB manufacturing site comparators, as I could find (so in total I'd say abt 50 different manufacturers). I know that once I go in the thousands and tens of thousands of pcs manufactured the price difference wouldn't matter, but until I go big, I need to make sure my design is working properly (even if this means 2 or 3 times lower clock speeds all around for the first couple of itterations). \$\endgroup\$ – vlex Dec 13 '16 at 7:27
  • \$\begingroup\$ Having said that, though, thanks for the input! I'm aware of the multitude of complications coming with lower layer count. If it were entirely up to me, I'd gone with 8 or 12 layers straight away, but it also kicks the price quite a bit, especially for someone trying to do it out of his own pocket. As I've said above - I even thought about using x32 twin-die chips, which would've saved a whole bunch of traces between both ranks, but 1 would've costed more than all 4 chips currently in use combined, even when calculating the price against 1k pcs. \$\endgroup\$ – vlex Dec 13 '16 at 7:29
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    \$\begingroup\$ @vlex you say that you need to make sure my design is working properly but running it a third of the clock speed is not going to prove that it is. Your real problems come when you run it at its intended speed. \$\endgroup\$ – Steve G Dec 13 '16 at 9:31

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