I'm looking to build a board using a xilinx xc3s50a fpga and using a static ram chip of some kind. Perhaps something such as the GSI Tech GSI71116A.
My worry is about the data lines of the ram chip. If I make a mistake on my verilog I could easily do a read cycle from the chip while outputting data from the fpga. I don't imaging setting a '0' on the fpga and a '1' on the ram chip, or the reverse would end well...
So basically I'm looking for information on what would happen? Is it likely to damage either or both chips or are they protected against this kind of thing by limiting the current? If the answer is no, could I protect myself by adding a small resistor in each data line to limit the current? While that would probably work electrically, I'm not sure what effect that would have once it's working and I need to send data at up to 100Mhz.
So basically, do I need to protect myself here? Can I protect myself? Or do I simply need to be really careful with my verilog code not to enable output on both devices at the same time?