2
\$\begingroup\$

We are working on a pipelined processor written in VHDL, and we have some issues with timing, synchronization and registers on the simulator (the code does not need to be synthesizable, because we are going to run it only on the simulator).

Imagine we have two processor stages, A and B, with a pipeline register in the middle:

  • Processor stage A is combinatorial and does not depend on clock
  • The pipeline register R, is a register, and therefor, changes its state at clock rising edge.
  • Processor stage B is a complex stage and has its own state machine, and, therefor, changes its state and does operations inside a VHDL process, governed by clock rising edge.

The configuration would be as follows

   _______   ___   _______
   |     |   | |   |     |
---|  A  |---|R|---|  B  |---
   |_____|   |_|   |_____|

With this configuration, there is a timing problem:

  • t = 0: A gets data, and does its operations
  • t = 1: At rising edge, R updates its data with the output of A.
  • t = 2: At rising edge, B gets the values of R, and updates its status and gives an output.

We would like to have B changing its state and generating an output at t = 1, but we also need the register in the middle to make the pipeline work.

A solution would be to update the R register on falling edge. But then, we are assuming that all processor stages run in half a clock cycle, and the other half is a bit useless.

How is this problem usually solved in pipelines?

\$\endgroup\$
  • \$\begingroup\$ Could you put the register before A? If it's a combinatorial stage, it shouldn't cause any strange behavior should it? \$\endgroup\$ – Sam Dec 13 '16 at 21:21
  • \$\begingroup\$ The advantage of pipelines is that so long as the execution is linear, all stages may be busy at the same time. It still takes multiple clocks to get through the pipeline, but given linear execution the next task is only one clock behind the previous task. \$\endgroup\$ – Tut Dec 13 '16 at 21:23
  • \$\begingroup\$ @Sam: This a small example. In the whole system, we will have 5 or more stages in the pipeline, and a few of those will have their own state machines. \$\endgroup\$ – markmb Dec 13 '16 at 21:32
  • \$\begingroup\$ @Tut: But, in this pipeline, stage B is two clocks behind stage A, because of the combination of the intermediate register and B's internal logic. But we don't know how to combine those two properly. \$\endgroup\$ – markmb Dec 13 '16 at 21:34
  • \$\begingroup\$ @markmb That maybe so, but why can't a combinatorial stage drive a state machine directly? If you have two state machines in series that's different, but I don't imagine a combinatorial stage needs a post register, have it drive the next stage directly, because unless it spits out gibberish while it's settling, you could get rid of one of you clock delays that way. \$\endgroup\$ – Sam Dec 13 '16 at 21:37
1
\$\begingroup\$

After talking to quite a few people, I think we found the proper solution to the problem.

The stage B, which has its own state machine, should not have a VHDL process activated on rising edge. It should have the state of the state machine as a signal that is stored on register R.

In more detail, these new signals should be added:

  • stat: current state of the state machine, output from R, input to B
  • state_next: next state of the state machine, input to R, output from B

Which means that state is changed for state_next each rising edge, and B can now work without a process.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.