This question is about SRAMs, specifically the ISSI IS61WV102416. This is an asynchronous SRAM. To write, we asserted CEn, put the data and address on the signal lines and then toggle the WEn signal high to low and then high. I think that the WEn could be called write strobe though I do not know what strobe generally means in this context.

Rather than toggling the WEn signal each time I put in a new data and address value, what would happen if the WEn is kept low and the address and data are changed simultaneously? I do not know if this will work since in physical hardware there will be a small difference in speed at which they toggle i.e all address and data lines will not change to new state simultaneousl. Therefore, I get the impression that the data may get corrupted in the memory. Is that correct?

I assume that if we don't have to toggle WEn each time new data is to be written, the data writing process shall speed up.


Yes, that is correct. If you change the address value while both CE and WE are asserted, you may corrupt any number of other locations in the memory as the change propagates through the internal row and column decoders at various speeds.

However, it is not necessary to toggle both WE and CE on every write cycle, since the actual write operation is controlled by the logical AND of both signals. You could leave one of them asserted continuously and only toggle the other when the address and data setup times have been met.

For example:

      _________________               ______________               _________
CE-                    \_____________/              \_____________/

WE-   ___________________________________________________________________
      ____      ________________________      ________________________
addr  ____XXXXXX________________________XXXXXX________________________XXXXXX
      ____                 _____________                 _____________

Note that in the datasheet, the address setup time tSA is relative to the leading (falling) edge of CE- (or WE-, whichever occurs last), while the data setup time is relative to the trailing (rising) edge. The address setup time is zero, but it still means that the address cannot change while CE is asserted. Both the address and data hold times are relative to the trailing edge.


Static memory chips will generally behave as though they sample the data input continuously as long as the write strobes are active. The data input will generally need to stabilize some time before the strobes are released, and might need to remain valid for some time after that, but there is generally no requirement that the data be valid before the start of the strobes.

If an address bit were to change while the strobes are active, the typical effect would be to complete a write at the old location with whatever was on the data bus at the time, and then start writing the new location. Provided only one address bit were changed at a time, this could easily be useful behavior. Memory chips do not generally justify such behavior, nor indicate how long the data for the first address would need to be valid before and after the address change.

  • \$\begingroup\$ Caution that changing the data lines at the same time as the address bit (as indicated by the OP) may trash the data in the previous location as hold times may be violated. I don't see a case that matches this in the datasheet. \$\endgroup\$ – Tut Dec 14 '16 at 21:49
  • \$\begingroup\$ @Tut: If the address lines change too soon after a data line changes, the old location might not reflect the data change even though it preceded the address change. If the data changes too soon after an address change, the change might alter the old location even though it follows the address change. If the setup and hold times for an address change were the same as those for releasing a write strobe, a write scheme that latched an address and a data byte, asserted strobe, changed the LSB of the address, latched the new data byte, and released strobe, could be faster than one which had to... \$\endgroup\$ – supercat Dec 14 '16 at 22:16
  • \$\begingroup\$ ...release and re-assert the strobe between the two bytes, but chips specs generally don't guarantee that such a pattern would be usable with the same setup/hold times (or any, for that matter). \$\endgroup\$ – supercat Dec 14 '16 at 22:16

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.