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On schematic below LDO U4 is disabled and U2 is not powered. Can the high output from U1 feed U2 inadvertently through the ESD protection diodes on U2's input?

schematic

simulate this circuit – Schematic created using CircuitLab

Assume that U2's input protection is implemented this (rather standard) way:

schematic

simulate this circuit

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ESD diodes can be a drag

You are correct that U2 can be powered this way -- I've seen this before when trying to hook programming cables up to otherwise unpowered circuit boards, aggravated by the typical order of connections where GND is connected first and disconnected last. While it won't necessarily trigger latchup as C2 will be mostly charged when the Vcc is turned back on, it can be quite aggravating as U2 may run when it shouldn't.

There are a couple possible fixes. If U1 and U2 are on separate boards, mating the GND connection between the boards last works around this problem -- it's what I did to avoid this for things like programming cable hookups. If U1 and U2 are on the same board, or the connector mating order needs to be GND-first, a suitable isolator (if this is a low speed digital signal, a jellybean 4N35 optocoupler and its associated resistors will do the job) will break the power path up as long as the output side supply/pullup is wired to U2's Vcc supply. (In the two-board case, this means it goes on the same board as U2.)

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    \$\begingroup\$ You don't need full-blown galvanic isolation; the grounds can be connected as long as all other potentially-high signals are disconnected (use a bus switch, analog switches, or any other buffer/driver with output enable). \$\endgroup\$ – CL. Dec 14 '16 at 9:50
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Yes. It is conceivable that U2 will power up and operate normally, or that some units out of a large lot will do so. But it is much more likely that U2 will attempt to power up and get into a bad state.

There are a lot of ways to deal with this. One is to put an isolation buffer near U1, and power the isolation buffer from the output of U4 (the same LDO that powers U2). Isolation buffers are specifically designed to have high impedance at all inputs when VDD = 0V. One example is fairchild/onsemi part number NC7WZ17P6X.

Another way, if the hardware supports it, is to just make the IO signal into an open-collector signal, and pull it up to the output of U4. You would have to insure somehow that U1 never drives it high or enables an internal pullup.

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This can trigger latchup when as shown if U1 is active high when U2 is powered up.

There are solutions, but yes this is a problem.

All the original PS/2 keyboard mouse cables on the original PC designs would latchup on insertion. Now they don't from design changes.

  • Opto-isolated is best for uncontrolled users
  • passive isolation can be 10k Series R but depends on bit rate/ cable signal integrity

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