I'm trying to get a Verilog design for interfacing with a PS/2 keyboard to work but I'm having very strange issues. I have a fairly simple always block which controls everything:
always@(negedge PS2_CLOCK) begin if(rst == 0) begin state <= READY; index <= 0; keycode <= 0; data <= 0; is_pressed <= 0; end else begin case (state) READY: begin state <= GRAB; is_pressed <= 0; end GRAB: begin if(index == 7) begin data <= (data >> 1) | (PS2_DATA << 7); index <= 0; state <= PARITY; end else begin data <= (data >> 1) | (PS2_DATA << 7); index <= index + 3'b1; end end PARITY: begin state <= DONE; end DONE: begin is_pressed <= 1; state <= READY; keycode <= data; data <= 0; index <= 0; end endcase end end
As you can see, this executes based on the negedge of the PS/2 clock but I'm not sure if that's a good idea. Every once in a while when I push a button on the keyboard, I fail to receive the data correctly and I think it's because of uncertainty in the clock signal. Here are two executions of the code when a button is pressed:
The first is of a correct execution of the state machine while the second has a clear disruption in the clock signal. In this case, it wasn't very damaging but if it occurs near the end of the data transmission, it often causes my machine to skip a state and get out of sync. Any advice would be greatly appreciated.