Does the async. and sync. reset signal follow the setup and hold time conditions of flip flop? If so how would they affect the output?
An async reset doesn't have a setup or hold time. Setup and hold are relative to a clock, an async input doesn't use a clock.
It will have a minimum active time, a propagation delay before the reset is reflected in the outputs and also a minimum idle time after being released. i.e. If you get a clock edge at exactly the time the reset goes away does it count as a clock or are you still in reset?
A sync. input will always have setup and hold times. For a reset these may be the same as for the data inputs or they may be different.
As with any timing, what happens when you violate the reset timing is undefined. It may reset, it may not reset or it could (and this is a long shot) change to some other non-reset state.
The asynchronous reset doesn't have a setup or hold time because it doesn't depend on the clock. There will be some propagation delay between when the reset is asserted and the output is guaranteed to be in its reset state.
Synchronous resets, since they are sampled on the clock, will have setup and hold times relative to the clock. Therefore timing closure will include your synchronous resets, but not your asynchronous resets.
In common usage (assert reset and hold it for a "long time"), the rising edge of reset isn't the issue. It's the falling edge of reset that matters. Cliff Cummings wrote a great paper that discusses the important practical issues with resets.