That "distance" affects the inductance, as does "distance" in free air versus over a plane. So, it depends. To take away the magic, lets examine the knobs and levers we can adjust.
Lets examine the "circuit", the CLC, the cap-inductor-cap, formed by the off-chip capacitor and the leadframe/bondwire/vias/PCBtraces inductor and the onchip depletionRegion+gateCapacitance...........all together forming a closed path for circulating currents in CLC PI resonator.
Its your job to identify that path (an IC with many VDDS and GNDs will have many such paths and many circulating/resonating paths), to identify the FAST edges (switching between ClassB pullup and pulldown, in an OpAmp, is FAST edge)that when correlated with the resonating paths will launch ringing/resonating, and to identify the DAMPENING.
Here is a PI CLC, of 100uF on left, 10nH on top, and 0.1uF on right, all with included parasitic ESR and ESL. The losses are 1milliOhm in each of C-L-C.
[ the greyed-out CLC on right is not part of simulation, but drawn to remind us of the dominant reactances]. Note the 20+dB peaking at 10KHz and 3Mhz.
Now, with optimal damping of 0.55 ohms (computed as sqrt(L/C) ), we see smooth plateaus of behavior, able to supply the surges as needed.
OpAmps have no power supply rejection at high frequencies, with 'high' depending on layout and quiescent current. If you need precision settling, you need to design ------design------ a VDD network with predictable ringing and with predictable dampening. You can seen performance flops of ICs that ignore this; one vendor merged a 24-bit ADC with a 33MHz MCU. The MCU must be SLOWED DOWN to 8MHz, before the ADC achieves the 24-bits. Why? Onchip ringing, triggered by the MCU clocking/movingprogram/movingdata, upsets the substrate and rails, never providing the QUIET TIME needed by the 24-bit ADC.
MCUs are more tolerant, we are told. But if you want a low-jitter MCU clock, pay attention to design-the-bypassing-and-grounding.
HighVoltage ICs will self-destruct, if you ignore inductance and dampening.
Warantee failures can result from many points in these systems, over temperature, over voltage (cap values change), as electrolytics age, and with initial component param variances of manufacturing. IC internal substrate resistances vary with doping fluctuations and temperature.