maximum distance between IC power pins and decoupling capacitor

Question

Since I introduced decoupling caps to my design, my auto-routing progress has dropped.

Currently my PCB track width is set between 0.24mm and 0.26mm (I'm trying to aim for 0.26mm depending on how routing goes).

What I want to know is what is the maximum distance allowed between an IC VCC/GND pins and the decoupling cap before performance of the IC degrades? I'm told to keep the capacitor as close to the IC as possible but when doing a single-sided board with the fewest jumper wires possible, keeping it ridiculously close is impossible.

Answer 1

Nobody can specify a maximum distance!

Even if in the datasheet 2mm is mentioned, doesn't that mean, that the chip won't work with 3mm. You won't even recognize a performance degradation or something like that in most cases. The longer the trace, the more will your supply drop. Currents are often not high, so thicker traces doesn't solve your problem sometimes. A bad design is often not that good in EMI measurements, if you have the possibility for a test.

Actually you can guess a little bit... Maybe you have output rise and fall times for your IC, you could calculate the resulting frequency and calculate the impedance of the trace. But again, nobody will tell you a maximum impedance, so do best effort.

However, you wrote you are designing a single layer board. Most of this boards i saw had the same mistakes: Everyone places a capacitor directly on a VCC pin, but the current comes back through the GND pin of the IC. So don't look for the nearest space for 100nF, look for the smallest current loop through the VCC AND GND pins. Standard logic devices don't have a very good pinout in my cases, because the supply pins are far from eachother.

If you aren't making your PCBs at home, consider to make more layers. More layers aren't soooo expensive this time and you get an much better design.

Answer 2

If you need decoupling caps, it's an almost certain bet that a single-sided board isn't going to work. You need a robust ground/Vcc system. At the least, a double-sided board with ground forming a relatively thick grid on one side, and Vcc on the other is a good way to start. Lay out the ICs on a rectangular grid. Set up ground completely surrounding the perimeter with horizontal traces (0.25 inches as a good start) running across the board from perimeter to perimeter. Vcc can be less rigorous, since the point of decouplers is to minimize transients WRT ground, not Vcc. Of course, a ground plane is even better, but the setup described was pretty standard back in the days of TTL DIP ICs.

Answer 3

Although I agree with the other answers for this question, I would also highlight that you will always be better off adding some decoupling to your board. Also, decoupling scheme depends on the frequency used. At higher frequency (>50Mhz) this gets very complex and it might even be better to spread caps out on the board as opposed to have them close to power pins (best results are given by measuring).

Another thing, never use auto-route unless you paid a lot of money for it. Most of the time it is better to route the board yourself.

Answer 4

That "distance" affects the inductance, as does "distance" in free air versus over a plane. So, it depends. To take away the magic, lets examine the knobs and levers we can adjust.

Lets examine the "circuit", the CLC, the cap-inductor-cap, formed by the off-chip capacitor and the leadframe/bondwire/vias/PCBtraces inductor and the onchip depletionRegion+gateCapacitance...........all together forming a closed path for circulating currents in CLC PI resonator.

Its your job to identify that path (an IC with many VDDS and GNDs will have many such paths and many circulating/resonating paths), to identify the FAST edges (switching between ClassB pullup and pulldown, in an OpAmp, is FAST edge)that when correlated with the resonating paths will launch ringing/resonating, and to identify the DAMPENING.

Here is a PI CLC, of 100uF on left, 10nH on top, and 0.1uF on right, all with included parasitic ESR and ESL. The losses are 1milliOhm in each of C-L-C. [ the greyed-out CLC on right is not part of simulation, but drawn to remind us of the dominant reactances]. Note the 20+dB peaking at 10KHz and 3Mhz.

Now, with optimal damping of 0.55 ohms (computed as sqrt(L/C) ), we see smooth plateaus of behavior, able to supply the surges as needed.

OpAmps have no power supply rejection at high frequencies, with 'high' depending on layout and quiescent current. If you need precision settling, you need to design ------design------ a VDD network with predictable ringing and with predictable dampening. You can seen performance flops of ICs that ignore this; one vendor merged a 24-bit ADC with a 33MHz MCU. The MCU must be SLOWED DOWN to 8MHz, before the ADC achieves the 24-bits. Why? Onchip ringing, triggered by the MCU clocking/movingprogram/movingdata, upsets the substrate and rails, never providing the QUIET TIME needed by the 24-bit ADC.

MCUs are more tolerant, we are told. But if you want a low-jitter MCU clock, pay attention to design-the-bypassing-and-grounding.

HighVoltage ICs will self-destruct, if you ignore inductance and dampening.

Warantee failures can result from many points in these systems, over temperature, over voltage (cap values change), as electrolytics age, and with initial component param variances of manufacturing. IC internal substrate resistances vary with doping fluctuations and temperature.