(This question occurred to me as a result of a different question here.)

I am usually fastidious about using decoupling capacitors near all power pins on ICs, large and small, analog or digital. I also use power and ground planes in PCB designs when possible. Generally, I try to use "good practice" in order to obtain reliable robust design. And, as far as I can tell, I've been successful.

The question is, what are the indicators of inadequate decoupling. Suppose I decided to not include the bypass caps at the power pins of a microcontroller or CAN transceiver, or something else.

There are some obvious indicators like the microcontroller spontaneously resetting, but there must be more subtle problems that I might not even see, or might not attribute to inadequate decoupling.

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    \$\begingroup\$ E M I springs to mind and susceptibility. \$\endgroup\$ – Andy aka Dec 15 '16 at 21:01
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    \$\begingroup\$ Power supply noise and ripple can couple into the signal path of analog circuits. 'Insufficient' decoupling would be the amount that results in an unacceptable level of noise coupling into your signal path. en.wikipedia.org/wiki/Power_supply_rejection_ratio \$\endgroup\$ – vofa Dec 15 '16 at 21:13
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    \$\begingroup\$ An indicator of inadequate decoupling would be ringing on the power pin, I'd imagine, due to unmanaged resistance and inductance, as well as its appearance on signal lines in and out of the device. \$\endgroup\$ – jonk Dec 15 '16 at 21:15

The symptoms are that most of the time everything will be fine, except sometimes it might not be. This can be data-dependent and very hard to reproduce.

Think about what's happening. Some chip suddenly increased its current demand. That caused its immediate power voltage to dip to some level where correct operation is no longer guaranteed. Even if not, the rapid change of the power voltage can cause trouble.

It is very hard to predict what exactly that trouble might be and at what threshold of voltage or derivative of voltage it occurs at. A data line may be temporarily interpreted in the wrong state. A flip-flop may get flipped. You don't know. Whatever happens is also a function of temperature, even uneven heating of the die. Try reproducing that exactly from one test to the next.

So the bottom line is things can get flaky. Maybe. Sometimes.

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    \$\begingroup\$ Whoever downvoted this, please explain what you think is wrong, misleading, or badly written. I'm not seeing it. \$\endgroup\$ – Olin Lathrop Dec 16 '16 at 11:52

The problems you get will vary a lot depending on the circuit used and the ICs used. I think your best bet is not to look for a specify problematic behavior of the circuit but to just check directly your voltage Vcc-GND on your scope as close as possible to the pin of your ICs.

During operation, you should see a flat line (pure DC voltage). If you get ripples, this is a clue that your decoupling is insufficient. You have to watch the voltage for all states your circuit can have and for an extended period of time. Ripples may appears periodically during a digital transmission only for exemple. Also, you must repeat this measurement for all ICs on your PCB even if they are on the same power bus.

The frequency of the ripple is very important as it will tells you what kind of capacitor you need to attenuate this specific ripple. For exemple, a low frequency ripple (below 1 kHz) will be filtered easily with an Aluminium Capacitor while a high frequency ripple (100 kHz or 1 Mhz) will be more easily filtered by a film capacitor or ceramic capacitor.

The amplitude of the ripple will gives you an idea of how much Farad your decoupling capacitor must be.

I think this method is the best to be sure your circuit doesn't suffer from poor decoupling instead of looking for strange/inconsistent circuit behavior.

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I have an easier and shorter answer:

When you have inadequate power you will get all kinds of weird problems that are usually not related to each other and that at first glance seems impossible to explain.

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This answer has 4 parts: jitter, power-gate-driver, ADC, and dataeye/PAM settling.

Your jitter specs will not be achievable, and you audio playback will be 'noisy'. Your phasenoise (aka jitter) will not be achievable, and your wireless link may not even synchronize; your bit-error or packet-error rates will be unacceptable; your duplex wireless links (intended to allow concurrent transmit and receive) will desense because transmitter close-in phasenoise will directly enter the portion of spectrum planned for the receiver.

For Power Driver ICs, given long GND and VDD leads, expect rails to initially collapse and then ring upwards, well above the VDD. By 5 or 10 volts, given 3cm of wire in leads of non-surface-mount Cbypass, or in absence of Ground Plane.


simulate this circuit – Schematic created using CircuitLab

Thus............self-destruction is a result of non-local bypass capacitors.

The resonant circuit is the lead inductances, and the on-chip C_well_substrate which is much smaller than the PCB Cbypass.

[edit] Regarding OpAmps and ADCs: Your measurements will show wide CODE SPREAD. Your opamp Vout will never settle, because their VDD is ringing at high frequencies and directly appearing on the OpAmp's Vout, to be digitized by ADC.

Your DataEye will be jittery, noisy, with non-flat tops, thus unremitting Inter Symbol Interference because the VDD is never quiet, has never settled, and that VDD ripple blasts right through the OpAmps to your signal because the OpAmps have 0dB PSRR at high (capacitor-lead ringing) frequencies.

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Supply Quality, Signal Integrity and margin to error!

If you already know what DVT means and perform a rigorous DFM,DFT and DVT on the design specs, then might wanna consider adding susceptibility reliability testing in your Design Validation Test plan. This includes: forcing the supply voltage to +/-10% limits and change crystal frequencies +/- limits to look for functional errors ( a.k.a. Schmoo plot test). - You do the same with hi/lo Temp and high %RH while injecting 1A pulse noise using a loop over the chips, looking for high impedance tracks with high impedance sources that cannot suppress the coupled noise.
- You may sniff board with a probe ground wire shorted to tip and look on a spectrum analyzer or scope with max sensitivity looking for noise and then inject noise back using a similar size loop from a 1 amp DIY pulse generator looking for functional issues.

Just like predicting when glass will shatter, binary systems in an analog world work perfectly until it breaks.

In order to understand the margin to symptomatic errors, one has to understand where noise comes and goes.

NOISE can be measured precisely and margin to error determined.

  • Sources: by Conduction, Induction or C coupling
    • conducted and/or radiated noise pulses or RF (>30MHz) or RF modulation, EH impulse fields (\$V=Ldi/dt\$), Capacitance ratio of load/coupling * Vnoise, internal demodulation of stray RF, Current coupling of adjacent tracks or nearby switched currents, common mode impulses coupled to unbalanced signal/gnd impedances, conducted supply noise & gnd return noise (aka ground shift), induced current \$ I_c=CdV/dt\$. It can also come from mismatched impedance ripple, where the rise time, \$t_R\$ is less than the prop. delay,\$t_D\$ on the track.
      • ESD to the gnd frame is also EMI that couples as ground shift or signal interference.
  • destinations: by Conduction, Induction or C coupling
    • PSRR: Every gate has a linear zone but unlike Op Amps with current source biases, the supply noise rejection ratio is nonlinear and is only critical during switching when both Nch and Pch drivers are active and not only injecting noise from either rail but conducting noise from either rail to the output. The differential supply noise between send and receiver implies a shift in threshold for the peak transition point in time which determines if multiple transitions may get thru the gate or not. When the switch is fully conducting, the track impedance/reactance may be much higher than the driver impedance which varies from 22 to 33 or 50 +/-20% Ohms for different voltage logic families. ( >300 Ohms for legacy CD4000 series)

Currents induced by large signal loops rather than shunted via nearby Cap to Vss:Vdd planes ( low inductance planes)

We can predict all binary communication results as an analog signal to noise ratio, SNR, with a probability function or a bit error rate. (BER).

  • So what is the SNR of Logic?
    • 40dB is good (<1%Vpp), 30 dB is fair, 20 dB is poor ( 10% Vpp)

  • Is there a bit error rate for any logic signal?
    • Yes but it is usually ridiculously large, until you do not follow Design Rules for Power / ground Planes and decoupling caps. Then it can become practically small if you neglect decoupling or too complex to calculate it so you always test it for margin before going into critical production where the costs of failure are high.
    • What is the signal ?
    • Vss, Vdd each treated as signal to some reference point near the receiving or sending chip.
    • What is Noise ?
    • A disturbance small enough that can't be easily seen but big enough to make your design fail, right after you ship it. ;) equivalent of "Blowing a raspberry"
    • Basically anything that is not a datasheet waveform signal.
    • What is the input threshold?
    • approx Vss/2 +/-x% or 1.3V for both 74HCTxx and RS-232 ( yes that's right)
    • What are \$V_{oh(min)}\$ and \$V_{ol(max)}\$ ?
    • these are the output levels (hi/lo) in IC Specs. for each logic family designed to offer good noise margin ( IN MOST CASES) It does not guarantee your system is EMI error free! These levels at stated current also define the driver Ron or \$RdsOn\$ impedance (max) for Hi(1) and Low(0). Typically 25 ohms in 74ALV logic and 50 ohms in 74HC logic.
    • What are \$V_{oh(min)}\$ and \$ V_{ol(max)}\$ ? These are the margin levels defined to guarantee reliable switching.
    • thus we see there is an inherent Noise margin in Logic design with the difference between these levels and the true Vth input switch threshold. For TTL you can measure this on any floating input with probe to ground. For CMOS you can test any gate with a negative feedback R like 1Mohm and observe this as the input threshold in the linear region with a voltage gain of at least 10 per internal gate. NAND gates are 3 stages of inversion so have a linear gain > 1k. This has been true across all CMOS families , that I have seen.


simulate this circuit – Schematic created using CircuitLab

Not shown is the 100 ohm ESR of the diodes and input capacitance and many other details.

There are excellent reasons to use a separate power and ground plane as close together as possible to increase the capacitance between then. The inductance of a square is the same for a whole PCB or a tiny chip capacitor. There are good reasons to choose 0.01uF over 0.1uF and visa versa if you get into choice of ceramic, SRF with synchronous clock currents and track layout. You can judge your noise problem by sniffing with a scope loop and measuring signal integrity of the supply without a ground clip using 1cm tip and barrel connections on 10:1 probe > 300MHz.

Learn to test your Noise Margin in every design

  • usually planned in the DVT even if you have lots of EMI experience. By close proximity (1cm) RF sniff test and noise injection.

Remember in your layout that the loop distance not only determines the path inductance but the area of the loop determines the EH field noise levels.

The functional symptoms of logic noise errors are anything unexpected, when you least expect it

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  • \$\begingroup\$ That's a lot of typing. \$\endgroup\$ – Supa Nova Dec 17 '16 at 18:41
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    \$\begingroup\$ It's hard to generalize without being thorough. A specific issue can be a 1 line answer. YOur response was well a little less than appreciative. Any questions? good luck. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 17 '16 at 19:12

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