I've been given a word problem, and I must make a state diagram followed by a state table.
The problem reads Design a circuit that has two inputs, clk and X and produces output O. X may change every clock cycle and the change happens at the falling edge. The circuit samples the input at every rising clock. O = 1 if the last values of X over the last three cycles were 101.
I don't quite understand this. I get that from S3, if X = 1, it goes back to S1, because when X is 1, we have made progress towards 101. However, why does S2 go to S3 when X is 0 and not 1? And why does S3 cycle back to S2 at 0?