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Is it possible to swap wires in data bus between CPU and DDR3 x16 memory for routing optimization?
So, for data lines depends on the correct order?
For example connect DQ0 on CPU to DQ1 on memory and DQ1 on CPU to DQ0 on memory.
Personally I think that this is possible, but I'm not sure.
(About address wires it is clear that they cannot be swapped, because address bus is used also as command)
Allowed bit and byte swapping for DDR2 and DDR3:
Also all command and adress signals must not be swapped.
LPDDR2 feature a mode register functionnality but it seems that nobody use this. Nevertheless if you want to be able to use it, first data byte should be routed straight. On DDR3 the mode register function is use through address bus, so you don't have to worry.
Finally some memory controller require some pins to be fixed for example with Freescale i.MX6. So read datasheet and application notes of your memory controller to be sure what you are allowed to and don't hesitate to contact the manufacturer.
Further reading: https://forums.xilinx.com/t5/Memory-Interfaces/possible-to-swap-pin-at-DDR3-memory-side/td-p/164558
Absolutely possible in generic case. We have done the same with DDR3 RAM and Intel atom processor. Unless we did shuffling the data bit order, there was no way (IMHO) to complete the optimal routing in 6 layers.
The bits gets shuffled while storing into RAM, but from processor point of view, it will remain intact.
Care should be taken, if memory is a shared resource.
As noted in other answers, bit swapping within a byte is permissible, but in DDR3 you should take great care if you are using write leveling.
Write leveling can ease the layout of DDR3 significantly if it is used correctly, but a drawback is that at least one designated bit (usually bit 0 in a byte) cannot be swapped.
Which bit is used needs to be evaluated for both the controller and DDR3 device and will usually be found in the datasheet for the DDR3 and commonly in the reference or user manual for a processor or controller.
