# Voltage level translation between +3V and +3.3V

In a project of mine I have two ICs that work at different voltages. IC_A at 3V and IC_B at 3.3V and they talk to each other through UART.

In my prototype I use a mosfet with two resistors for each signal in UART( TX, RX ) as a level converter.

My question is:

Could I omit the mosfet and connect them directly or with only a resistor in series? And if yes how to find the resistor's value? e.g.Ohms law?

edit: 3V and 3.3V are the theoretical voltages. When I measure them they are 2.85V and 3.3V...

• I have read the datasheets and have them printed in paper but I am afraid to connect the ICs because the 3V one has VImax=3V so 3.3V may kill it. If this is the deal I should stick with the mosfets. IC_B accepts 3V as high.
– Tedi
Dec 16 '16 at 22:48
• I don't mean to answer your question with another question, but seriously, why not run the 3.3V part at 3.0V? My money says there would be absolutely no operating difference. Dec 17 '16 at 7:05
• The part is a ATSAM4LC2A. In the datasheet says that if I am to use a USB peripheral I should power with 3.3V. The other part is a GSM that is powered from 4V but its pin output is 3V.. So I have no option. :(
– Tedi
Dec 17 '16 at 14:42

You actually don't care what the VCC or VDD voltage level is, but are more interested in the V(input lo) and V(input high) requirements for both devices.

For your 3 V and 3.3 V system elements the real questions are:

1. When driving the 3 V input from the 3.3 V element output can the output voltage be too high?

For many interface elements the input is advertised as 5 V safe, so for those elements the 3.3 V output can interface directly to the 3 V system.
I'd suggest there are no conditions where this would not work or cause damage.

Some logic has clamp structures in the input gates, so there is more to consider. For these elements it may look a bit like this:

Under these conditions (high signal) where the input diode clamps are planar diodes with a Vf of typically 650 mV you unlikely to get current flowing from the 3.3 V output into the 3 V elements VDD structure/supply.
For safety your could add a small value resistor to limit current.

1. When driving a high from the 3 V element will V(output high) meet the requirements of the 3.3 V element V(input high).

Since the V(output high) of the 3 V element will approach 3 V, this will easily meet the requirements which are likely in the 1-1.8 V level. You can directly connect the 3 V element output to the 3.3 V element input.

• I am trying to understand your answer but I am not aware of Vf. Is it some vital parameter in the daatasheets I should look up or is a voltage in the schematic you provided. Also thanks for the trouble posting this.
– Tedi
Dec 16 '16 at 23:14
• Ohhh!!!! Vf is the voltage drop of shottky's. My mind stuck for a moment. :)
– Tedi
Dec 16 '16 at 23:16
• There is no Schottky diodes in internal I/O pads in regular CMOS ICs. Making a Schottky barrier requires special process steps and is cost prohibitive. They are regular planar diodes. Dec 21 '16 at 5:11
• @Ali Chen. You are absolutely correct, they are no Schottky diodes....my bad. Fixed answer. Dec 21 '16 at 5:27

There is an important principle to consider here:

Even if they are operating at the same nominal voltage you need to worry about connecting one to another if they are operating from separate supplies.

Typically the abs max input voltage limits are Vdd to GND +/- 300mV. When one is off, that means that more than +/-300mV you are violating the absolute maximum spec. If current is not limited, damage can occur, especially when power is re-applied to the one that is off.

There are a few ways to deal with this (in increasing order of cost and performance:

1. A series resistor (or voltage divider) will limit the current and, if a divider, lower it it a bit.

2. A BJT or MOSFET can be used with a pullup to the respective supply. BJTs are a bit cheaper and more rugged.

3. A voltage translator chip with separate supplies (both suppliers go to the chip) can be used. Some chips will accept voltages from 1.8 to 5.5 on either side, or other wide ranges. For example 74AVCH2T45 translates one bit in each direction from any supply 0.8~3.6 to any supply 0.8~3.6 with propagation times < 10ns in either direction.

To use a resistor, you have to be satisfied with relatively slow propagation delays. For the 3V->3.3V you can almost certainly just use a series resistor. Most 3V-ish devices are CMOS and most are happy with 0.7Vdd or 2.31V for a 3.3V supply, so you would still have 600-700mV of noise margin, which is plenty.

If speed is not an issue, something like 10K is nice, and limits the input current to a really safe level. To go the other way, you might be able to get away with 10K again, but it would be nicer to divide it down by about 10%, so 10K/100K:

simulate this circuit – Schematic created using CircuitLab

Speed wise, if the capacitive load was quite large (say 100pF) due to cable or whatever, then the time constant would be 1us. Probably not a problem for a UART, at least at 115k baud or less.

Of course the transistors invert the signal and the resistors (and most voltage translators) do not, but you knew that.

• @JackCreasey Most micros don't limit the current on their outputs, they'll happily output enough current to damage their drivers, as many a hapless arduino user has found out. Dec 17 '16 at 4:44
• @JackCreasey - The damage that Spehro talks about is not about how much or how little current the powered up driver can directly inject into the powered down part. Anything over a few mA injected into the powered down part can find a stray circuit path on that part to a PNPN or NPNP junction stack. It takes very little injected charge to prime one of these SCR type junctions into a "biased as on" state. Then when the unpowered part is turned on this primed SCR can conduct current right inside that part; not from that powered output which is just providing the bias. If you are (continued) Dec 21 '16 at 11:19
• (continued from above) lucky the SCR will conduct only a small amount of current and fizzle out as the part becomes fully powered. A little more bothersome is that the SCR causes some localized logic upset in the part but just at a limited current flow. In this case the whole system must be powered off to remove that latched up logic. In the catastrophic case that SCR latch just happens to end up across an internal circuit path between the Vdd and Gnd. If that happens the current flow may only be limited by the on chip metalization or doped silicon resistivity and (continued again) Dec 21 '16 at 11:28
• (continued from above) can lead to silicon destruction. Such destruction can be short term in as in a localized meltdown or could be a long term silicon stress. In the long term case failure would likely happen if the latchup were a repeating event. It is not safe to ever pass this effect off as "only happening with older chips". It is a real effect and the reason that all chip manufacturers specify the abs max ratings for pins relative to the Vdd and Gnd which incidentally applies whatever voltage level may exist on that Vdd pin. I've seen all types of the latchup over the years. Dec 21 '16 at 11:36
• @JackCreasey - Another thing to keep in mind is that as ICs get more and more complex, in some cases with billions of transistors, there are more and more possible logic paths that can get "pre-biased" by charge injection. Dec 21 '16 at 11:40

If the $V_{oh}$ (voltage provided on the output) of the driver is greater than the minimum $V_{ih}$ (voltage required on the input) of the receiver, you are good.

There are two different things you need to be thinking about here.

Firstly there is the low-voltage device talking to the higher voltage device. As @BrianCarlton has mentioned, if the voltage put out by the low voltage device for a HIGH value is above the HIGH threshold for a logic input (if $V_{OH}$ is above $V_{IH}$) then it can be directly connected. If not then you will need some way of raising the voltage above $V_{IH}$.

The second is the high voltage device talking to the low voltage device. This is more about the risk of overloading the input than any logic levels (though you may just want to check out the LOW logic level thresholds in the same way as for the HIGH levels in the other direction).

You should first check the absolute maximum ratings for the low voltage device to see if the higher voltage is going to be too high. If it's within the absolute maximum for an input (usually something like Vcc + 0.3V) then you should be OK, though for sustained HIGH values it could be "dodgy".

Most devices have some form of protection on the inputs (though not all, so check first) in the form of diodes between the pin and ground and Vcc. This allows any excess voltage above Vcc (or below ground) to be fed through to the relevant rail instead of entering the IO pin (diode clamping). These only have limited current capacity though, and it's the adding of a resistor to the input that helps in this scenario - limiting the current to avoid damage to these diodes (assuming they exist - you could always add your own as well).

Some data sheets include a "maximum over-voltage current limit" in their ratings. That is basically the current rating of these diodes. You can use that to work out the lowest value of resistor that would still be safe. In general, though, higher is better, but not too high as to adversely affect the shape of your signal. For UART data that's not much of a problem since you are working at relatively low frequencies.

However, for the price of, say, a BSS138P and a couple of 10K resistors, is it really worth taking the risk?

• Well the risk is not worth taking for sure. I just read the datasheets. IC_A(VCC=3V) detects high at 3V-2.55V and low at 0.45V-0V. IC_B(VCC=3.3V) is a microcontroller ATSAM4LC2AA but must be powered at 3.3V. I read the microcontrollers datasheet in page 1136 but there are many parameters to write here. I got a little confused. There are min and max values for each VILmin VIMmax. :(
– Tedi
Dec 16 '16 at 23:05
• Sorry my mistake I figured it out.....
– Tedi
Dec 16 '16 at 23:09

Everything is quite simple. You don't need to do anything, and just connect both circuit directly. The rail difference is actually within normal 10% tolerance of LVCMOS-33 interface.

Both devices are CMOS devices. The CMOS devices have logical (switching) threshold somewhere in the middle of voltage rails. And the switchimg point scales ratiometrically with supply voltage. So one device will have it at 1.5V, the other at 1.65V, plus-minus 300-400mV in worst case ever. The standard for Low-Voltage CMOS-33 standard defines safety margins and calls for 2V level as minimal input HIGH. Therefore, as long as both sides drive their respective signals nearly rail-to-rail (as usual for low-loaded CMOS circuitry) and HIGH is above 2V and LOW is below 0.8V, everything will be just fine.