# What determines the orientation of a coupling/blocking capacitor in an amplifier circuit?

"In analog circuits, a coupling capacitor is used to connect two circuits such that only the AC signal from the first circuit can pass through to the next while DC is blocked. This technique helps to isolate the DC bias settings of the two coupled circuits. Capacitive coupling is also known as AC coupling and the capacitor used for the purpose is also known as a DC-blocking capacitor."

Here is an example of use of it:

Below another example from a question on this website:

And here is an example from an electronics text book:

What determines the orientation of the coupling capacitors here? Is that the Vcc voltage? But if so, the last example does not follow the first two. Which one is correct and why?

edit:

Below a polarized cap is used with an AC signal. There is no DC level. As you see the voltage across the cap is alternating from +7V to arounf -7V? Is this acceptable?

• Other than the (+) side being connected to whichever side has the more positive voltage? Probably not much. If you use a non-polarised capacitor then you don't even have to worry as a non-polarised capacitor is totally symmetrical unlike normal electrolytics. – Sam Dec 18 '16 at 18:46
• do you mean the last one is wrong then? – user16307 Dec 18 '16 at 18:48
• The input cap on the last one should have the positive terminal connected to the transistor base. – Vladimir Cravero Dec 18 '16 at 18:53
• Hmm, quite possibly, put more than a few % rated voltage the wrong way through a polarised electro and it starts to be have more like a resistor (and does some permanent damage). Although having said that, I have seen some people use that symbol to indicate any electrolytic capacitors and a (+) to indicate a polarised one, but personally I think that just confuses people as it adds unnecessary ambiguity. – Sam Dec 18 '16 at 18:55
• @Sam please see my edit question – user16307 Dec 18 '16 at 19:23

Depends on the DC level of both sides: If one side is higher then (+) terminal should be connected to that point.

Let's examine this on the example circuits shown in your question:

1) At point A, DC level is 0V. At point B, DC level is $V_B = 12 \cdot 10/91 = 1.32VDC$, so (+) terminal of the cap should be connected to B.

2) At the point on the left side (i.e. input side), there is no DC level shown, so we'll suppose it 0V. At the point on the right side, DC level is $V_x=24\cdot 10/20 = 12VDC$, so (+) terminal should be connected to the junction of R2 and R4.

3) The coupling cap at the input is not an electrolytic. So there's no polarity. Likewise, output coupling cap is not an electrolytic as well. But if it was an electrolytic, since the DC level at the output (i.e. at the junction of RC and output transistor's collector) is non-zero then (+) terminal should have been connected to that point.

hth.

• Thanks but a few more questions here: 1-) Doesn't the last circuit have "polarized capacitor" symbol? so the book is wrong i guess(?) 2-) And secondly is that the DC level matters only or the voltage across the polarized cap? Please see my edit. – user16307 Dec 18 '16 at 19:21
• Well, some books use the symbol in the last example as a non-polarized cap. They put a + symbol as well, when indicating an electrolytic capacitor. Anyway, 1) if it's really an electrolytic in the last example then it will be problematic when placed that way. 2) My answer was based on the circuits you have shown. But I should have generalized. Of course it depends on the voltage across the cap, not only the DC level. Think about the DC level and voltage swing: If negative swing is larger than positive DC level then it will be dangerous for an electrolytic. ... – Rohat Kılıç Dec 19 '16 at 4:20
• ... Now look at the circuits in your question. Is there any possibility for negative voltage swing to be larger than positive DC level across the caps? Make the necessary analysis and you'll find the answer. Now let's look at the edited part and simulation results: Since you're using an electrolytic and there's no DC level, it will be problematic during the negative voltage swing across the cap. I recommend you to use non polarized cap there. Also, capacitor's reactance and 100R resistor forms a voltage divider. That's why you see +/- 7V swing instead of +/-10V. – Rohat Kılıç Dec 19 '16 at 4:30

But if so, the last example does not follow the first two

The last example shows a polarized capacitor at the input and it is the wrong way round. It clearly contradicts the output coupling capacitor so the 3rd circuit has problems.

In addition to this, the AC signal developed across a polarized decoupling capacitor should not be very much or you will run the risk of reverse polarization problems. It's impedance should be low compared to the bias resistors following it so that the AC develops across them and largely DC appears across the capacitor.

Feed a higher voltage low frequency signal to the input at your own risk.

My personal philosophy is use non-polarized capacitors where this problem might arise.