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How to test synthesizability and time characteristics of an isolated Verilog module which can have its own interface much wider than pins number of choosen FPGA?

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Timing characteristics can only exist after your design has been applied to a specific FPGA – an Ice40HX will have a different timing than a LatticeSC ; not even mentioning that the two of them have different logic units and the same verilog would be synthesized to two different netlists.

However, you should be able to synthesize your code for specific FPGA without placing it on an actual bitstream.

On top of that: The number of pins on the package has absolutely nothing to do with the architecture that you implement inside the FPGA. I don't know how you've got that idea.

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    \$\begingroup\$ You would have a hard time placing a design that needs 400 IO's in an FPGA with only 200 pins. \$\endgroup\$ – The Photon Dec 19 '16 at 1:53
  • \$\begingroup\$ @ThePhoton that's true, but OP asked about synthesizability. And a Verilog module doesn't have IO pins – the signals are connected to those using either special Verilog IO (pseudo)modules or in a pin mapping file (haven't worked with the proprietary Lattice tools yet). You're referring to placeability, which comes a few steps later :) \$\endgroup\$ – Marcus Müller Dec 19 '16 at 1:55
  • \$\begingroup\$ I just tried to synthesize a project with a single Verilog module with wide parallel-to-parallel interface and synthesis has been failed due to low io number, not slice capacity. All I want is to check if my code will work on chosen FPGA at desired speed before coding a real interface modules. \$\endgroup\$ – e_asphyx Dec 19 '16 at 3:18
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    \$\begingroup\$ @MarcusMüller, remember that beginners might not know the difference between synthesis, place&route, mapping, etc. All they know is the clicked "build all" (which they might think of as "synthesize") and the tool produced an error. And if no constraints file is provided, the tool might arbitrarily try to fit the design into the chip with a more-or-less random mapping of top level module I/O's to chip IO pins (I haven't used Lattice tools enough to remember if they'll do this, but Xilinx ISE certainly will). \$\endgroup\$ – The Photon Dec 19 '16 at 17:06
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    \$\begingroup\$ @MarcusMüller, I think the tool designers have the idea that people will design the FPGA logic, then build a board around that. So the tool can assign pins "optimally" and the board designer would use those assignments. In practice every project I've worked on has done the board design first and then designed the FPGA logic as layout is being completed and boards are being fabbed. \$\endgroup\$ – The Photon Dec 19 '16 at 17:40

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