I want to build a FSK modulator and demodulator, the center frequency is 4.234MHz +-175kHz, FL is 3.951MHz, FH is 4.516MHz, mean data rate will be 564.48kbit/s. After searching the web, I found that FSK modulator can be build with DDS or PLL, demodulator can be build with PLL or complete software(DSP). Honestly, that's all the information I got. Do you have better recommendation on how to build this kind of FSK modulator and demodulator? Thank you!

  • \$\begingroup\$ when you googled did you add the word 'circuit' to your search? \$\endgroup\$ Dec 19, 2016 at 11:36
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    \$\begingroup\$ Hm, did you do the math? This is the rare case of an FSK system where the baud rate is higher than the frequency deviation. But anyway, the way you ask this is pretty much a "I need a full lecture on digital communications, can you put that into an answer?". Which might be a bit much. Yes, I'd do that in DSP completely, but I'm also an outspoken SDR person. Maybe tutorials.gnuradio.org and the suggested reading page help you. \$\endgroup\$ Dec 19, 2016 at 11:45
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    \$\begingroup\$ 4.234 MHz + 0.175 MHz = 4.409 MHz and not 4.516 MHz! And ditto what @MarcusMüller said about the data rate. \$\endgroup\$
    – Andy aka
    Dec 19, 2016 at 11:53
  • \$\begingroup\$ @Andyaka stumbled across some UAT aircraft transponder mode that did exactly this – having a symbol rate so high that if you mixed the "center" between the two subcarriers to 0Hz, you'd have something like 0.6 periods of the low or high carrier per symbol. Suuuper awkward to synchronize and decide. However, once I realized that this is 1950's tech, the approach was simply not to mix the center to baseband, but simply letting both carriers have positive frequencies>symbol rate in the downconverted signal. From there, it was a simple 2-bandpass-Filter PFB of an intentionally undersampled signal. \$\endgroup\$ Dec 19, 2016 at 12:26
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    \$\begingroup\$ @Andyaka: The +/- 175 kHz is the tolerance on the center frequency. It is (obviously) not meant to be a different way of specifying the modulation. \$\endgroup\$
    – Dave Tweed
    Dec 19, 2016 at 23:54

1 Answer 1


Some thoughts but certainly not a full design: -

The modulator is a lot simpler than the demodulator. For each data bit, the number of oscillation cycles is as follows: -

  • Bit = high, number of clock cycles is 4.516 MHz divided by 564.48 k = 8.0 cycles
  • Bit = low, number of clock cycles is 3.951 MHz divided by 564.48 k = 7.0 cycles

So, for the modulator, you need two clock frequencies that are chosen depending on what logical level the data bit is. The clock frequencies should be phase synchronous in that when the last clock is despatched and the bit changes, the lower clock immediately starts at a transition from low to high. This is important but not hard to achieve.

For the demodulator there is more dificulty due to the counts of cycles being very close. So I would be tempted to use a much higher-speed counter that can be used to measure the period of each received pulse. A PLL could be used - it might be possible but with only 7 or 8 clock cycles to distinguish between logical 0 or 1, it might be a bit tricky for a beginner.

Having said that, a PLL could be used to obtain the average of the two FSK frequencies - you then have a centralized reference frequency that can be used with appropriate logic circuits to decode a 0 or 1. This only works if the two frequencies produced are phase synchronous as previously described. However, the data to be sent should be scrambled so that there are no long periods where the data rests in one logical state or the other.

As for performance in the presense of noise, the lack of cycles for each bit means there could be some problems.

  • \$\begingroup\$ ha, you're also taking the "let both frequencies stay at positive frequencies instead of doing the downmixing to minimal-bandwidth baseband)". True, 4.5 MHz is something we can easily sample directly nowadays. \$\endgroup\$ Dec 19, 2016 at 12:28
  • \$\begingroup\$ @MarcusMüller just read your comment below the answer and thought it sounded familiar!! \$\endgroup\$
    – Andy aka
    Dec 19, 2016 at 12:30
  • \$\begingroup\$ Thank you both, it seems I have much to understand... Need a while. \$\endgroup\$
    – iouzzr
    Dec 19, 2016 at 13:18
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    \$\begingroup\$ THAT is over the top just use a clock that dives by 8 and 7 to give the two frequencies \$\endgroup\$
    – Andy aka
    Dec 20, 2016 at 14:01
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    \$\begingroup\$ Correct, you have to find the common point in time when they both momentarily sync up and that's where you allow the data to reinfluence the choose of frequency. So you need to do some logic design to detect that point then clock the data through to change or maintain that shift in frequency but, remember this site is not a full design service and we have to draw this question to a conclusion somewhere but, for little pieces of design, new questions can be raised. \$\endgroup\$
    – Andy aka
    Dec 20, 2016 at 15:43

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