To answer your question of how registers actually work in a CPU, it depends on the CPU. I've reverse-engineered several old microprocessors and they use a variety of register circuits.
The Z-80's registers simply store a bit in two cross-coupled inverters. The value is changed by forcing the inverters to a different value with a higher current signal. The bus is connected to all the registers, and the bus control signals select which bus is read or written. The register cell is a 4-transistor SRAM cell.
The 8085's register file is similar to the Z-80, except to read a bit, the signals go through a differential amplifier. This allows the signals from the register to be weaker, allowing the register to be denser, but makes the read circuit more complex.
The 6502's registers use a different circuit. Again two inverters are used, but a pass transistor in the loop allows the circuit to be broken. Another pass transistor (with an opposite signal) is used to store a new value into the inverter. (You can think this as multiplexing either the old value or the new value.) Each 6502 register is implemented slightly differently, since they all have special purposes.
The earlier 4004 and 8008 use a 3-transistor DRAM cell for registers (probably because of Intel's experience building DRAMs). The chips include a refresh counter and amplifiers to constantly refresh the data in registers.
These register designs are different from NAND gate designs, since they use pass transistors rather than Boolean logic, so they aren't what you want to use. For your specific questions:
Selecting registers should be independent of the address bus, which is used for external memory. You probably don't need to clear the accumulator first.
D flip flops will probably be easiest for you to use.
You can have a reset pin to clear the registers. You'll need to clear the PC so you start execution at a predictable address, but you don't need to clear the rest.
You can use a MUX to select a register for reading, but probably a decoder to select a register for writing.
I'd suggest designing (and perhaps building) your CPU from higher-level components than NAND gates. Then when you get it working you can break down components to NAND gates.