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The Setup:

I am currently prototyping a wheatstone bridge setup to measure small resistance changes. I don't have the sensor I'll be using yet, so I've simulated it using trim pots. I am using a SAML21 xplained board. I have side A and B of the wheatstone's bridge connected to two of the SAM's internal OPAMPS with programmable gain. I then feed the OPAMP outputs into the 12 bit ADC in signed differential mode.

The Problem:

I have tried a few different configurations and I can't seem to make heads or tails of it. A bridge voltage of 2mV(or and imbalance of 100 ohms between R2 and Rx if you prefer) is created from a 1V source voltage. When referenced to ground as the OPAMPs do when it is passed through them, this is actually about 580mV for side A and 578mV for side B. The gain is set to 3, so when passed to the positive and negative ADC inputs it comes out to about 2.32V for the positive terminal and 2.31V for the negative.

What I get out is about -1000 ADC counts. This makes no sense to me. The positive end is set up to the node of higher potential. So I tried changing the reference voltage. It was set up to an internal 1V ref and I changed it to one labeled INTVCC0 with the comment "1/1.48VCC reference". The result then came out to 203 counts. Finally I tried another reference INTVCC1 commented "1/2VCC (only for internal VCC > 2.1V)". This resulted in about 700 counts.

To my understanding of the differential measurement, the reference voltage should not affect it since the difference between the two is all that matters.

I have tried changing the bridge voltage by a decent factor on all these references and the changes I see make no sense.

The Question(s):

Basically I am a bit lost as to what the ADC is telling me, and what changes I can make to get the desired measurement. I understand single ended well enough and what the reference voltage does there, but I cant seem to manage this transfer to differential. Can anyone point out problems or things to check?

Side question, could I take the line I'm using for the negative input and instead connect it to an external reference pin for the ADC and use the other input as the positive pin in the single ended input mode? If so, how is that different from what I'm currently doing?

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  • \$\begingroup\$ If you swap your two inputs, do you get +1000 counts? If so, you may be misinterpreting your sign. \$\endgroup\$ – WhatRoughBeast Dec 20 '16 at 1:10
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Any differential ADC (and the op-amps too) will have a common mode rejection ratio (CMRR). So The common mode voltage (the average of the + and -) terminals will affect the output.

All op-amps also have an input offset voltage that essentially adds to your differential input voltage when computing the output. The input offset may be just a few microvolts for very precise amplifiers, or it may be a few millivolts for most common op amps. ADCs have a similar parameter which would be the zero offset, which is typically several LSB.

Put mathematically, one could model the output as...
Vout = G * (V+ - V- + Vos) + C * (V+ + V-)/2
Where...
V+ is the non inverting input.
V- is the inverting input.
C is a factor edpending on your CMRR. It would be 1/100 for 40dB of CMRR, and 1/1000 for 60dB of CMRR, etc.

So for example if the common mode rejection ratio say 60dB then you would see a change in the output measurement that is equivalent to 1mV of change at the differential input voltage for every 1V of change in the common mode voltage.

If your input voltage range is just a few mV then input offset and CMRR need to be considered or your measurement will be washed out by component tolerances.

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  • \$\begingroup\$ The internal op amps have +/- 3.5mV Vos and the gain set resistor accuracy is not stated; in my experience that is usually about 10% for integrated things such as this. \$\endgroup\$ – Peter Smith Jul 16 '18 at 15:35
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To test your configuration you should be sure to use shielded twisted pairs, STP or UTP as a minimum.

  • design a loop back self test with DAC outputs to input A and B and sweep the output and calbirate your erro. It should be resolved by gain and offset error.

  • then verify if your settings are correct and according the manual on Fig 41-8

Vout = (V2-V1)*Gain + Ref

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  • \$\begingroup\$ The " @community "' person who down-voted without comment is lacking competence in ADC debug skills if he thinks my method of calibration to determine the transfer function will not reveal the problem. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 28 '19 at 9:43

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