I am designing a circuit with a Spartan6 FPGA and the documentation for the FPGA specifies 4.7uF (0805) and 0.47uF (0402) capacitors for decoupling. As I really do not want to solder 0402 capacitors if I can avoid that, I would like to use 0805 or 1210 size capacitors for this. Would their performance at high frequencies be different from those that have smaller packages?

The max in/out frequency is ~300MHz

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    \$\begingroup\$ A an aside, the BGA variants of Spartan-6 require [at least recommend] 0201 capacitors located between the balls. \$\endgroup\$ – Nick Alexeev Dec 20 '16 at 3:14
  • \$\begingroup\$ @NickAlexeev I'm using the TQFP version as it is available and soldering BGA is not fun at all. \$\endgroup\$ – Pentium100 Dec 20 '16 at 3:40
  • \$\begingroup\$ SRF always increases with smaller size parts. Std 1206 0.47uF is ~ 5MHz at 10mohm \$\endgroup\$ – Tony Stewart EE75 Dec 20 '16 at 4:16
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    \$\begingroup\$ A caution regarding small package ceramic capacitors. Their capacitance can drop significantly with DC bias and can be much more than people may realize. Be sure to look up data for the specific part number, not a family datasheet. (info may be looked up on manufacturer's websites) See: Ceramic Capacitors FAQ See also: Why 47uF capacitor drops to 37 uF, 30uF or lower \$\endgroup\$ – Tut Dec 20 '16 at 19:14

Yes, it makes a difference.

A larger package will generally have a higher parasitic inductance, leading to a lower self-resonant frequency and higher impedance at high frequencies:

enter image description here

(image source: electronicdesign.com)

For an 0.1 uF capacitor at 0402 size, the resonant frequency is typically in the 10-20 MHz range.

  • \$\begingroup\$ FYIO, yesterday I discovered that also Electrolytic Capacitors have some parameters that change with physical dimension. For example, from PW series Capacytors from Nichicon, the impedance at 100kHz change with diameter: See here, for an image. \$\endgroup\$ – Antonio Dec 20 '16 at 7:59
  • \$\begingroup\$ @Antonio These are OK for SMPS but not for decoupling Spartan CMOS chips . Actually ESR = uF/volume is a power series for a given Vr and family of electrolytics. obrazki.elektroda.pl/7094755900_1482262954.jpg \$\endgroup\$ – Tony Stewart EE75 Dec 20 '16 at 19:44

The reason for max ESL is from V=Ldi/dt >> V(ripple)=Vr= ESL * dI/dt where dI comes from CMOS cap load spike with driver ESR 25~50 Ohms into load and Miller Cap in pF with slew time dt and from any CMOS logic drivers, Ic=CdV/dt this is a "dynamic" current spike with Miller cap and input+stray cap loading thus dI(L)=I(C) so ...

Vr=ESL C dV/dt²

Ripple can be large and is critical dependant on ESR ( thus current limit of driver) ESL of track, C load and ESR of C load with high Q resonance. Many variables but in this example 50Ω thus 100mA short circuit current from 5V but only rated for 50mA. with 1 inch of FR4 at 10nH/" and 2pF/" so nearest decoupling cap is 1 DIP package away at 1". The result is > 10% noise but assumes no ground plane. enter image description here

For ultra low ESL the aspect ratio for L/W must be low. 603, 1206 are both 2:1 but 306 is reverse geometry to 603 and thus nearly 1/4 the inductance and almost twice the SRF.

It is usually best to use 3 caps spread apart by no more than 3 decades due to ESR,SRF properties. The bulk largest size depends on step load & ESR of LDO for load regulation error and the bulk cap reduces this error. Next short term transients > 1us where PSRR is poor is the intermediate cap from 0.1 to 1uF then the smallest cap for RF slew rates values must be >100x the Coss or effective switched capacitance of all synchronous gates in [mA/ns] for charge transformer ratio in ripple reduction. For RF in the GHz range these require careful selection well below 100pF unless sufficiently high rated SRF.

For example of ~40:1 ranges 47uF, 1uF, 0.01uF
ALternatives use many (>>10) in parallel with a low aspect ratio of L/W of same value such as 0.1uF of carefully selected low ESL part.

in general, but specifically don't use General purpose caps use low ESR/low ESL and verify layout and specs. Don't guess.

enter image description here

By the way. this 306 has the same size 60 thou termination coductive pads as 1206. This trick to soldering them with a 67 thou tip (1/16) is to quickly tack one side then solder the other then resolder the 1st side with a toothpick holding it down on (abrasively) cleaned pads. This works well for 603 parts as well and 402 is best done with a hot air method with paste. and tool to hold in place if tombstone issues arise...

These are also excellent 1206 Acrylic caps. http://www.digikey.com/product-detail/en/cornell-dubilier-electronics-cde/FCA1206A105M-H3/338-4076-1-ND/5700231

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    \$\begingroup\$ That's all true information, but its answering a different question than what was asked. \$\endgroup\$ – The Photon Dec 20 '16 at 4:52
  • \$\begingroup\$ It shows exceptions to the generalization where smaller size has higher SRF. Consider it an alternative answer but you can disagree if you dont understand my logic. \$\endgroup\$ – Tony Stewart EE75 Dec 20 '16 at 4:57
  • \$\begingroup\$ Actually @ThePhoton I tried to address both solderability and SRF and the bigger picture of low ESR broadband for the supply to yield lowest ripple to a step load pulse. \$\endgroup\$ – Tony Stewart EE75 Dec 20 '16 at 5:12
  • \$\begingroup\$ Is there a list of "average" ESLs based on size somewhere? The FPGA manufacturer has specified max allowed ESL, so I guess i can probably find a physically bigger cap with reverse geometry and the same ESL (or use multiple in parallel). \$\endgroup\$ – Pentium100 Dec 20 '16 at 6:57
  • \$\begingroup\$ @Pentium100, you can calculate it from the capacitance and the resonant frequency. \$L_p \approx 1 / \omega_r^2 C\$ \$\endgroup\$ – The Photon Dec 20 '16 at 15:51

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