"The biggest problem with asynchronous resets is that they are asynchronous, both at the assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost."

Source: Page 18 , section 5.4 of http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf


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The assertion timing doesn't matter because the whole point is that all the elements of the circuit enter a valid/known reset state. It generally doesn't matter what order they do it in, only that the final state is predictable.

De-assertion is a problem because if some flip-flops come out of reset before others, they may start changing state while others are stuck in the reset state. This can lead the entire system to be in an invalid state.


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