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I'm trying to use one of my design's internal signals in my testbench. I already know how I would do it in Verilog:

Goertzel i1 (
// port map - connection between master ports and signals/registers   
);
.
.
.
always @ (posedge i1.en) //do something

en is the enable signal I generate in my sistem, it is a signal declared in the top module, which is created in one element of the system, and then distributed to some of the other elements via port maps.

So, in VHDL testbench, I want to do something like:

uut: Goertzel PORT MAP (
          RST => RST_s,
          CLK => CLK_s,
          X => X_s,
          Y1 => Y1_s,
          Y2 => Y2_s
        );
.
.
.
wait until "/goertzel_tb/uut/en/" = '1';  //path to variable, read in Questa

What is the correct syntax? Or is there a way to do this?

EDIT: Tried this: Declared spy_en signal within TB file, and then did:

spy_en <= << signal.goertzel_tb.Goertzel.en : std_logic >>;

Questa gives errors.

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Not exactly what I was looking for, but it does the trick as it should! How can I get internal signals to testbench in VHDL 97 and ISim?

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The syntax you are referring to was added in VHDL-2008. If your simulator supports it, you can do what you want as described here. ISim probably does not have any VHDL-2008 support.

Without VHDL-2008 your only options are simulator vendor specific functionality, using global signals as in your answer, or with debug ports in your entity.

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