Since in the outer space the NSEU will be more common than in the earth, how the electronics in space vehicle is tacking the issue. I feel a solution will be existing for some decades but on google I got some information about single bit error corrections only. It does not mention any prevalent techniques.
There are several aspects.
Neutrons (or high energy radiations) can wear materials by moving atoms or making transmutations... and the electronics may eventually fail permanently.
There can be also transitory perturbation where the effect is merely that some electric charges are displaced making a glitch in circuits.
There are a few mitigation techniques:
Redundancy. Several devices doing the same thing. Sometimes only one is powered to save energy : "cold redundancy". (as a comparison, in aeronautics, there is also redundancy for safety, but all systems are powered : "hot redundancy" for a faster reaction time and because power constraints are less strict)
Specialty technology. For semiconductors, some techniques are less sensitive to aggression : Things as SOI, "sillicon on saffire" are better because the volume of material where a particle can have an effect on the circuit is smaller. There are many other techniques, I'm not an expert. Nowadays there is a trend to limit the use of funky materials to save money : More redundancy, more fault tolerance instead of unobtainium components.
Error Detection and Correction and triplication techniques. By using error correction codes (hamming, Reed-Solomon...) you can be able to detect and correct errors in memory areas, registers.. By triplicating your design and using voters, you can be tolerant to a single upset somewhere.
System design. Be able to automatically reset and restart your computer without compromising the mission. Independence of functions. Self monitoring...
Finally, there are statistics. The radiation flux is different in aeronautics, low earth orbit, deep space probes and probes getting close to the sun. You get failure probabilities, FMEA analysis, and over-design enough to get an acceptable probability of failure.
I think what you are concerned is how during the communication, and data transmission, the RX and TX between Centran CPU and secondary CPU of scientific load, the system detects that there was an event of false bit. Usually it is due to communication protocols which are used in these system have few flags in telecommands which protect against these errors. For example SpaceWire or 1553. They have bit count and CRC.
Also if you have a system which detects, for example ions, than you copy the electronics of the first circuit and have 2 detectors, one for real measurements and the las one in case there was a false event. (At least thats what I did in my project). I had a system which detected the events in 3 different states (MEV intervals) and I had a fourth one to detect false detections.
If it's not what you ment than sorry for the wrong answer.