There is a need to have a group of signals arrive simultaneously to their respective destinations, given that they start their journey at the same time.

However, due to physical constraints it is not possible to have them routed on the same layer, breaking routing symmetry. In order to calculate their lengths so that flight time is equal, propagation times are needed. I have formulas for microstrip and stripline propagation speeds, but I don't have any for vias. Does anyone have any information about this?

PS:I am aware that nearby ground vias are required for the return path to find a way to switch reference planes.


Via impedance can be approximated by its capacitance and inductance. From pages 257 to 259 of High-Speed Digital Design:

$$ C_{\text{via}} \text{[pF]}=\frac{1.41 \epsilon_r T D_1}{D_2-D_1} $$ D1: diameter of pad surround via [in.]
D2: diameter of clearance hold in ground plane(s) [in.]
T: thickness of PCB [in.]
\$\epsilon_r\$: relative electric permeability of circuit board material

The 10%-90% rise time degradation for a 50\$\Omega\$ transmission line due to this capacitance will be \$ {T_{10-90}}=2.2C_{\text{via}}(Z_0/2)\$.

$$ L_{\text{via}} \text{[nH]}=5.08h\left[ln\left(\frac{4h}{d}\right)+1\right] $$ h: length of via [in.]
d: diameter of via [in.]

Inductive reactance is \$ X_L \text{[}\Omega\text{]}=\pi L_{\text{via}}/T_{10-90} \$. I'll leave making the link between XL and T10-90 degradation to someone who has actually done this.

Total via delay is estimated in the sequel, High-Speed Signal Propagation, on pages 341 to 359, to within an order of magnitude, with the following comment:

It makes no sense to define, or to attempt to measure, the inductance of a via without also specifying how the attached traces bring current through it, and how the planes carry the returning signal current.

$$ t_v=\sqrt{L_VC_V} $$ LV: incremental series inductance
CV: incremental shunt capacitance

To properly measure [CV], first measure the static capacitance to the reference planes of a configuration that includes an input trance of length x, the via, and an output trance of length y, where both x and y greatly exceed the clearance-hole diameter. The lengths x and y are measured to the center of the drilled via hole. Then separately measure the static capacitance of a similar trace of length x + y (with no via and no clearance hole). [CV]... is the difference between your two measurements.

[LV] is defined similarly, but with each trace shorted to the reference plane at its far end. Arrange your equipment to detect the loop inductance of the path entering trace [x where it is shorted] ..., passing through the short-circuit at the far end of [y]..., and returning through the reference planes to the equipment, [where x is shorted].

The pi model can be applied for a more accurate model. Place half of CV in each cap and the full LV in the inductor. These approximations are only good for frequencies above the onset of the skin effect -- at least 10MHz and preferably 100MHz.

If your via is so large compared to the signal risetime that you require anything more than a simple pi-model for the via, then it probably isn't going to work very well for a digital application. Use a smaller via.

  • \$\begingroup\$ Doesn't the formula \$ T_V = \sqrt{LC} \$ show the time delay? \$\endgroup\$
    – Jon Watte
    Mar 7 '12 at 7:56
  • \$\begingroup\$ According to this, if the vias are 6 mil drill, 18mil pad diameter, 28mil plane opening (antipad) and 60 mil length, this gives \$C_{via} = 0.7\mbox{ }pF\$, \$ L_{via}=1.5\mbox{ }nH\$, so \$T_V=35\mbox{ }ps\$. This means \$35\mbox{ }ps / 0.06" = 580\mbox{ }ps/inch\$. A LOT slower than the microstrip (\$150\mbox{ }ps/inch\$) or stripline (\$180\mbox{ }ps/inch\$). Why is this if the dielectric material is the same, and supposedly \$V = c/\sqrt{Ere}\$ ? \$\endgroup\$
    – user3812
    Mar 7 '12 at 8:20
  • \$\begingroup\$ Small vias are generally inductive in digital circuits, so they slow down rise times. Note that the \$L_V\$ is the added inductance taking into account the entire current path, while \$L_{via}\$ is not -- it's the partial inductance, so they're not the same. If calculated \$L_V\$ should include \$L_{via}+L_{path}+L_{mutual}\$. The formula \$v=c/\sqrt{Ere}\$ contains \$Ere\$, which is determined from the geometry of the stripline. Changing the current path geometry, such as with a via, changes \$Ere\$. \$\endgroup\$
    – tyblu
    Mar 7 '12 at 14:15
  • \$\begingroup\$ Here, the author of the two mentioned texts goes a bit further: sigcon.com/Pubs/news/6_08.htm \$\endgroup\$
    – tyblu
    Mar 7 '12 at 14:16
  • \$\begingroup\$ Remember, you can use TeX in comments too. Just surround your equations with \$. \$\endgroup\$ Mar 7 '12 at 19:18

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