If you have a photodiode detector that can output a digital 1 or 0 on every pulse then creating a trigger that outputs on every 3rd pulse is not that hard.
Make a state machine that essentially counts to 3 and then resets.
Let there be a clock signal that is the output of your photodiode detector.
Let there be a 2 bit state variable that counts the pulses (lets call it C).
Let there be a trigger output. Lets call it T.
An HDL description for the state machine would look like...
if rising_edge(clock) then
if C = "00" then C <= "01";
elsif C = "01" then C <= "10";
else C <= "00";
T <= C = 00;
You could of course synthesize that HDL code on a CPLD directly. Alternatively you could use a few 74-series logic chips to implement the logic.
C(0) <= C(0) NOR C(1)
C(1) <= (C(0) NOR C(0)) NOR C(1)
T = C(0) NOR C(1)
So you would need a quad NOR gate, and two D-Flip-Flops.
Also, as some have suggested, you could use the pulse detector to clock a 3 stage shift register arranged in a circle. Your trigger would be the output of one of the three register stages.
The shift register would need to be preloaded with the value "100". After the first pulse the value would shift to "010", after the second "001", and then after the third it would go back to "100". So you would have a 1 on your trigger every third pulse.