# What does “open drain when programmed for the wait function” mean (in micro controller spec language)?

So I am reading the Zilog Product specification for the Z8440/1/2/4, Z84C40/1/2/3/4 serial input/output controller (here it is http://www.zilog.com/docs/z80/ps0183.pdf).

And there is one sentence I dont understand the meaning of:

Here is the schematic with the leg marked:

I can understand, for example, TxDA, TxDB. Transmit Data (outputs, active High) which to me means that the pin will have voltage (it will be pulled high), when the controller will starts sending data to the output channel.

But what does it mean by "open drain when programmed for Wait function"? What is this drain and how to open it?

In this particular case, machine based on Z80 chipset may have several sources of wait signals - for example DMA, video processor, machine core core logic - and you just connect all these open drain outputs together, connect pull-up resistor to the resulting line, and have AND function of everything connected. If any of signals goes low (or all go low), resulting signal will be low. In terms of current flow, if open drain/open collector output is deactivated (to be simple - output transistor is turned off) there's minimal current flowing through it. If it is active, then current is flowing through pull-up resistor and collector-emitter junction, and this current is limited by this pull-up resistor.