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How can I check the value of array input in Verilog? I tried this code but, I got an error "op_code is not a constant"

module mutlti_proccessor(data_out, flags, data_1, data_2, op_code);
    input [7:0]data_1;
    input [7:0]data_2;      
    input [3:0]op_code;

    output [7:0]data_out;
    output [4:0]flags;
    /* flags[0]:ZF "Zero Flag", flags[1]:SF "Sign Flag", flags[2]:CF "Carry Flag", 
       flags[3]:OF "Overflow Flag", flags[4]:COF "Compare Flag" */

    wire carry;

    /* Set falgs to zero */
    assign {flags[0], flags[1], flags[2], flags[3], flags[4]} = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };

    if(op_code==00000)
        Ripple_Adder RA1(data_out, carry, data_1, data_2, 0);


endmodule


Where Ripple_ADD is another module that sums up two 8-bit numbers.
Note: there is no clock.

Thanks ....

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  • \$\begingroup\$ I'm getting an error A is not an constant \$\endgroup\$ – White159 Dec 28 '16 at 9:24
  • \$\begingroup\$ Okay I am editing ... \$\endgroup\$ – White159 Dec 28 '16 at 9:27
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Your problem lies in the line of code:

if(op_code==00000)
     Ripple_Adder RA1(data_out, carry, data_1, data_2, 0);

You don't seem to have understood that Verilog is a "Hardware Description Language", not a procedural programming language. It does not execute code line by line, but rather is synthesized into hardware based on what you are describing.

You are trying to use an if statement incorrectly. What your code is describing is that if the op_code is 0, then create some hardware called Ripple_Adder. However, what happens if op_code is not 0? Does it need to infer the adder? Should it delete the adder?

Simple answer, it can't - the hardware is fixed at synthesis, you can't add or remove bits of it when running. This is why it is complaining about op_code not being a constant - it doesn't know whether or not Ripple_Adder should be included or not.

The solution, is to always include the hardware, and then infer a multiplexer to select whether or not the output of it is used. Something like this:

wire [7:0] ripple_data_out; //Output data for the ripple adder
Ripple_Adder RA1(ripple_data_out, carry, data_1, data_2, 0); //Infer the ripple adder

always @ * begin
    case (op_code)
        5'b00000: data_out = ripple_data_out; //If the op_code matches, connect ripple_data_out to data_out through the mux.
        //... Add more cases here for other op_code values ...
        default: data_out = 8'b0;
    endcase
end
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  • \$\begingroup\$ Yes, I am a beginner "learning basics" ...:) Thanks .. \$\endgroup\$ – White159 Dec 28 '16 at 10:05
  • \$\begingroup\$ @White159 I'd suggest reading through this tutorial. I found it quite useful when I first started with Verilog. \$\endgroup\$ – Tom Carpenter Dec 28 '16 at 10:06
  • \$\begingroup\$ I am sorry ... I have another question: If we have a variable to be set in multi_proccessor module, CF: carry flag, which is set inside Ripple_Adder module, how can I do it? \$\endgroup\$ – White159 Dec 28 '16 at 10:52
  • \$\begingroup\$ @White159 Same way as the data_out, infer a mux. \$\endgroup\$ – Tom Carpenter Dec 28 '16 at 10:54

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