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I have an OLED display with a current reference input to control brightness.

Absolute maximum brightness is achieved by sinking 12.5uA, which is usually accomplished by a resistor to ground.

I wish to control brightness from my MCU, which has a programmable current-mode DAC. The DAC is capable of sinking up to 64uA, but I expect the OLED to be damaged at that setting.

I don't want to rely on software alone to protect the device. How can I scale the 64uA maximum sink of the IDAC to the 12.5uA maximum sink of the display?

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    \$\begingroup\$ Put a resistor in series. \$\endgroup\$
    – Andy aka
    Commented Dec 29, 2016 at 16:43
  • \$\begingroup\$ Which MCU and OLED display, and what are their supply voltages? \$\endgroup\$
    – Bruce Abbott
    Commented Dec 29, 2016 at 17:46
  • \$\begingroup\$ In much the same way as you can build a resistive voltage divider, you can also build a resistive current divider. \$\endgroup\$
    – Sam
    Commented Dec 29, 2016 at 22:49
  • \$\begingroup\$ @Bruce, the OLED display is UG-2864HSWEG01, and the MCU is EFM32JG1B100F256GM32-C0 . Both are running on 3.3V. \$\endgroup\$
    – Craig Iannello
    Commented Dec 30, 2016 at 2:38
  • \$\begingroup\$ Your OLED display requires 7.0-7.5V Vcc (either supplied externally or generated by its internal DC/DC converter) and its datasheet implies that the IREF pin has 7V on it (12.5uA with 560k resistor = 7V). Since your MCU is only rated for 3.3V you will need a level shifter to control the current. \$\endgroup\$
    – Bruce Abbott
    Commented Dec 30, 2016 at 6:55

1 Answer 1

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Your MCU output is limited to 3.3V maximum, but the OLED display's IREF input sits at ~7V. Therefore as well as reducing the current you will also need to extend the voltage acceptance to >7V. Here's one solution:-

schematic

simulate this circuit – Schematic created using CircuitLab

The MCU's IDAC is configured to source up to 64uA, which is converted to a voltage by R1. OA1, Q1 and R2 create a constant current sink. The op amp maintains the same voltage across resistor R2 as R1, but since R2 is 5 times larger the current through it is 5 times smaller (ie. 12.5uA vs 64uA). Q1 is rated for 45V so 7V is no problem for it.

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  • \$\begingroup\$ Thanks Bruce. This is much more elegant than a digital pot. FYI, in my application, since I am using the internal DC-DC, for which they recommend a 390K resistor on IREF, the implied VREF is 4.875V. What might I need to change in your design? \$\endgroup\$
    – Craig Iannello
    Commented Jan 1, 2017 at 13:06
  • \$\begingroup\$ I see that I wouldn't have make any change to account for that. I ran a sweep simulation of this on CircuitLab. Very cool. Sweeping IDAC from 0...64uA in 0.5uA steps, there is a perfect ramp on IREF from ~0 to 12.5uA .. but for IDAC=500nA there is a strange spike of ~32uA on IREF. Is that a real outcome, or some quirk of the simulation? \$\endgroup\$
    – Craig Iannello
    Commented Jan 1, 2017 at 13:36
  • \$\begingroup\$ It worked perfectly in LTSpice, so I think it is a simulation quirk. Try reducing the step size to 50nA. \$\endgroup\$
    – Bruce Abbott
    Commented Jan 1, 2017 at 18:51

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