Mapping is generally done with dedicated hardware in silicon, usually under the auspices of the CPU. Let's look at your four phrases really quickly:
- IO Mapping
- Memory Mapped IO
- Port Mapped IO
My gut says that your usage of memory-mapping and IO mapping stems from the dual memory spaces of x86-based system -- the 64K of IO Space that is essentially deprecated, and then the much larger memory-space, which I think ranges into the exabytes now with 64-bit machines.
EDIT: I'm going to add this paragraph to my answer, guessing that what you're asking is more microcontroller (PIC, AVR, etc.) focused. I touched on that a bit to answer your number four question. The mapping / addresses here are basically fixed by the chip architects, and generally there's an address decoder / memory management unit (not in the strict MMU sense) that sends data to the right place on the internal bus. I.E., if you write to an UART control register, it affects the flip-flops that are physically responsible for those bits, if you read from a SRAM address, it returns the data directly from that.
Either way, mapping is the same general task -- take a specific address, and give it special meaning / route it somewhere. For instance, on a x86-platform, I/O space address 0x3F8 points to the register for the serial port on the system. When you write to or read from this address (outb()/inb()), you are physically changing the state of 8 bits (implemented likely as SRAM or flip-flops) that contain data on that serial port.
Likewise, for memory-mapped I/O, you may have a PCI device that requests some amount of memory. I could design a device where if you write a byte to a specific address, that changes the state of 8 LEDs -- 0x00, all off, 0xFF, all on. Your MMU (memory management unit) is responsible for recognizing that the memory address you wrote too is destined for something on the PCI bus.
I'm not going to dive into virtual memory here -- in modern OSes, it's generally only kernel code / privileged code that has the opportunity to directly read/write from physical memory addresses. There is infrastructure / abstraction layers built in to control this access for user applications. You could read up on page tables, for example.
So, back to your questions --
1) How I am supposed to visualize the mapping?
Just that -- a mapping. It's a map that tells you how to get from your start (an address, say, 0xE0000000) to the destination (perhaps a PCI device, perhaps a specific location in physical RAM).
2) Is the mapping done on the RAM?
No. Physical RAM -- say, at the lowest level, an individual capacitor representing a single bit in DRAM -- is one of the many destinations that could be mapped too. Every single memory address does not necessarily correspond to a physical bit stored somewhere.
If you have a processor that has an external address/data bus (or some other large parallel bus), then reads/writes will be directly translated into traffic on that interface -- most folks these days will use SPI/I2C/other serial protocols, but it was not uncommon to have large embedded systems where parallel SRAMs would be attached via a 8 or 16-bit parallel interface (AD0-AD15).
3) If yes, Isn't it memory itself? How does the processor know about it?
On x86 systems, most of the low-level management of the system memory map, which has some 20+ years of legacy on it, is done by your BIOS firmware, and then the OS initialization afterwards.
4) Is this mapping done when I switch on the Controller or is done by the person/Company that manufatured the controller?
There are fixed mappings in silicon (very true for embedded microcontrollers), where you can peruse the datasheet and get fixed addresses for control registers, peripherals, etc. The architects of the chip designed a memory map that made sense to them, and usually leaves provisions for different models with differing peripherals / amounts of memory (i.e., a 32KB and 64KB model of the same chip may have all their registers / peripherals in the same locations, and only the memory address for the RAM is different).
For more sophisticated systems where things can move around (like PCI plug and play), the memory address allocation is dynamic and executed by software.