Happy New Year! I've recently completed a metal detector project (see my recent questions) and I've been going back over some of the parts I didn't fully understand first time around.
This question relates to the differential peak detector section and my simplified spice model equivalent. I was trying to compute the small signal gain according to some standard equations (i.e., Rc/2Re) and comparing them to the spice output, but was confused by what I saw. I was expecting a very large gain (>600 according to the standard formula), but instead spice was reporting a rather disappointing Ad of < 90.
It took me a while to figure out that Q1 (see spice image) is saturated and I'm guessing the typical formulas don't apply. Unless I've made a stupid error, I think I know "why" Q1 is saturated: the output impedance of the DC reference is (by my calculation) around 260k; this high impedance coupled with a high value collector resistor is starving the transistor of current and forcing it into saturation. The transistor wants to draw 700uA/2, but it can't.
So, assuming my analysis about the arrangement is correct, why would the author deliberately saturate Q1? Is this a common pattern and what are the advantages of doing this? Also, given that the standard formulas no longer work it seems, is there any "pencil and paper" way to calculate the AC gain at the output? (by this I mean, what heuristics might the author have had in his head when putting the arrangement together) Many thanks!