I have lessons about VHDL in one of my university class and I have to write simple entity
which will generate clock from 1MHz source. I'm using CoolRunner-II CPLD Starter Kit with ISE Webpack 13.1.
When I run simulation of my code, I've got odd results. I have no idea, where the problem is. My VHDL entity looks like this:
entity clock is
Port ( clk_in : in STD_LOGIC;
clk_1M : out STD_LOGIC;
clk_500k : out STD_LOGIC;
clk_100k : out STD_LOGIC;
clk_1k : out STD_LOGIC;
clk_1hz: out STD_LOGIC);
end clock;
Input is 1MHz signal from oscilator and I want to create 1MHz, 500kHz, 100kHz, 1kHz and 1Hz output signal. I defined several signals:
signal c100k: std_logic_vector(3 downto 0) := (others => '0' );
signal c1k: std_logic_vector(9 downto 0) := (others => '0' );
signal c1hz: std_logic_vector(9 downto 0) := (others => '0' );
--
signal c500k_out: std_logic := '0';
signal c100k_out: std_logic := '0';
signal c1k_out: std_logic := '0';
signal c1hz_out: std_logic := '0';
And finally, my code is:
process (clk_in) begin
if clk_in'event and clk_in = '1' then
-- 500kHz
c500k_out <= not c500k_out;
end if;
end process;
process (clk_in) begin
if clk_in'event and clk_in = '1' then
-- 100kHz
c100k <= c100k + '1';
if c100k = X"A" then
c100k <= (others => '0' );
c100k_out <= '1';
else
c100k_out <= '0';
end if;
end if;
end process;
--
-- Code for 1kHz and 1Hz is same as 100kHz
--
clk_1M <= clk_in; -- Clock source 1Mhz
clk_500k <= c500k_out; -- Clock source 500kHz
clk_100k <= c100k_out; -- Clock source 100kHz
clk_1k <= c1k_out; -- Clock source 1kHz
clk_1hz <= c1hz_out; -- Clock source 1Hz
When I run simulation, I got this odd results:
What is wrong with my code?