I have a circuit that makes uses of a decoder to command the latch line of 8 latches. To avoid spurious latching that could occur in transitions, I disable the decoder output while I change the input address.
I'd like (in order to work faster) to get rid of this mechanism. My input addresses are just counting (000 001 010 011 ... 111), so I was wondering if there was an IC that could fit my need, something like
8 output lines, with at most one line i reading 1
1 clock line which would do i = (i + 1) % 8 on an edge
1 reset line which would do i = 0 on an edge
Something like a synchronous counter + decoder without the transitional problem described above in one chip.
Does it exists ?