I've read some very good answers on this subject in questions such as this one and also here.

I'm just a hobbyist designing a very simple PCB, however I still have a few questions about how best to layout the decoupling capacitors on my PCB. It's primarily for WS2811 chips which are LED drivers. I'm using 0805 sized capacitors as I'm not short of space. I could even put the caps on the underside of the board if necessary.

Currently my design stands at this:

PCB Design

The top layer is VCC and the bottom layer is GND. The VCC and GND pins are on different sides of the chip (U1). Currently I've run the data signal (maximum 2MHz) to layer 2 and back. This probably isn't the best way to do it?

Is it even necessary for the GND of the decoupling capacitor to be connected to the same via as the GND of the chip?

  • 2
    \$\begingroup\$ I presume the thermal pad is grounded, in which case put the cap as close as possible to VCC, and then route the ground through the thermal pad. \$\endgroup\$ Commented Jan 2, 2017 at 22:54
  • \$\begingroup\$ @TomCarpenter, you should post that as an answer. It's exactly what I was going to say. \$\endgroup\$
    – The Photon
    Commented Jan 2, 2017 at 23:10
  • \$\begingroup\$ Is R1 a series resistor on the power to the LED driver chip? That seems like a bad idea to me. You want the connection from C1 to the power plane to be as solid as possible. If you have some very sensitive ADCs on this board or something else that requires very low noise then that sort of trick may be needed but for a medium-low speed digital system all you're doing is adding the potential for things to go horribly wrong. \$\endgroup\$
    – Andrew
    Commented Jan 3, 2017 at 9:09
  • \$\begingroup\$ As per the WS2811 datasheet it goes 5V -> R1 which goes to both C1 (to GND) and VDD (pin 8 of U1). \$\endgroup\$ Commented Jan 3, 2017 at 17:29

1 Answer 1


As TomCarpenter says, in this scenario, a good solution would be to move the capacitor near the VCC pin (pin 8 of U1, I think), then connect its ground side to the thermal pad under the chip, and connect thermal pad directly to the ground pin (pin 4).

Is it even necessary for the GND of the decoupling capacitor to be connected to the same via as the GND of the chip?

Ideally, the ground pin/pad of the capacitor should be connected by as short a trace as possible to the ground pin of the chip, and the VCC pin of the capacitor connected by as short a trace as possible to the VCC pin of the chip.

The idea is to make as small a loop as possible from VCC, through the chip to GND, and through the capacitor back to VCC. This will generally minimize the equivalent inductance of the connection between the chip and the capacitor.

If your soldering process is capable of it, you might prefer to use smaller capacitors than 0805, because they have lower internal equivalent inductance. (on the other hand, using a larger package will allow getting a capacitor with higher voltage rating, and thus generally less reduction of capacitance due to applied voltage)

Reducing the inductance (in the connection to the chip, and internal to the capacitor itself) increases the resonant frequency of the connection to the capacitor, so it increases the frequencies at which the capacitor continues to provide a low impedance for currents drawn by the chip.

  • \$\begingroup\$ Thanks for the good explanation. What I've actually managed to do is choose the wrong footprint for the U1 chip. The chips I'm using don't actually have a thermal pad, so there isn't anything under the chip. In this case, would it be best to route the signal under the IC, and then move the cap closer to the IC so the traces to VCC and GND are shorter? Or is there a different placement I should consider for the capacitor? \$\endgroup\$ Commented Jan 2, 2017 at 23:40
  • 1
    \$\begingroup\$ Yes, I'd tend to move the cap near pin 8, and route the ground from the cap under the chip to pin 4. A wide trace will also help slightly to reduce inductance. Honestly, though, at 2 MHz none of this is super critical. But still, good practice for your next design, maybe. \$\endgroup\$
    – The Photon
    Commented Jan 2, 2017 at 23:46
  • \$\begingroup\$ With a via directly under the centre of the chip (i.e. in between GND (pin 4) and the cap)? \$\endgroup\$ Commented Jan 3, 2017 at 0:05
  • \$\begingroup\$ I'd put the via as close to pin 4 as possible (you have to have it far enough away that that there is a solder mask dam between the chip's pad and the via so that solder doesn't get sucked down the via when you're doing assembly). Also there's no law against multiple vias (and I'd recommend multiple vias if this were a higher-frequency design). \$\endgroup\$
    – The Photon
    Commented Jan 3, 2017 at 0:07

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