0
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I have extended SR flip-flop to have four inputs and four outputs.

It works well once an input has been pressed but I'm not sure how to set the initial state.

I saw a schematic online where a capacitor was placed in parallel with the pull down resistor that connects to my preferred initial states NAND gate. On my breadboard this appears to work. On the simulator however, if I leave the initial state and return to it I get a "convergence failed" error.

My question is, does the "convergence failed" error highlight a real problem with my circuit, and if so is there a better way to set the initial state of the circuit?

Circuit diagram: enter image description here

My netlist code is below:

$ 1 0.000005 10.20027730826997 50 5 50
151 688 80 800 80 0 2 0 5
151 688 208 800 208 0 2 5.000000000000002 5
151 688 336 800 336 0 2 5 5
151 688 464 800 464 0 2 5 5
w 800 80 800 160 0
w 800 208 800 288 0
w 800 336 800 416 0
w 800 464 800 544 0
162 800 80 848 80 1 2.1024259 1 0 0 0.01
162 800 208 848 208 1 2.1024259 1 0 0 0.01
162 800 336 848 336 1 2.1024259 1 0 0 0.01
162 800 464 848 464 1 2.1024259 1 0 0 0.01
r 848 80 912 80 0 1000
r 848 208 912 208 0 1000
r 848 336 912 336 0 1000
r 848 464 912 464 0 1000
g 912 80 912 96 0
g 912 208 912 224 0
g 912 336 912 352 0
g 912 464 912 480 0
R 352 96 352 64 0 0 40 5 0 0 0.5
w 688 64 416 64 0
w 688 192 416 192 0
w 416 64 416 96 0
r 352 96 416 96 0 1000
s 416 96 416 144 0 1 true
g 416 144 416 160 0
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w 688 448 416 448 0
w 416 448 416 480 0
s 416 224 416 272 0 1 true
s 416 352 416 400 0 1 true
s 416 480 416 528 0 1 true
g 416 272 416 288 0
g 416 400 416 416 0
g 416 528 416 544 0
w 352 96 352 192 0
w 352 192 352 320 0
w 352 320 352 448 0
r 352 192 416 192 0 1000
r 352 320 416 320 0 1000
r 352 448 416 448 0 1000
r 688 128 752 128 0 1000
g 752 128 768 128 0
r 688 256 752 256 0 1000
r 688 384 752 384 0 1000
r 688 512 752 512 0 1000
g 752 256 768 256 0
g 752 384 768 384 0
g 752 512 768 512 0
d 640 80 688 80 1 0.805904783
d 640 96 688 96 1 0.805904783
d 640 112 688 112 1 0.805904783
w 688 128 688 112 0
w 688 112 688 96 0
w 688 80 688 96 0
d 640 208 688 208 1 0.805904783
d 640 224 688 224 1 0.805904783
d 640 240 688 240 1 0.805904783
d 640 336 688 336 1 0.805904783
d 640 368 688 368 1 0.805904783
d 640 352 688 352 1 0.805904783
d 640 464 688 464 1 0.805904783
d 640 480 688 480 1 0.805904783
d 640 496 688 496 1 0.805904783
w 688 512 688 496 0
w 688 496 688 480 0
w 688 480 688 464 0
w 688 384 688 368 0
w 688 368 688 352 0
w 688 352 688 336 0
w 688 256 688 240 0
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w 608 336 640 336 0
w 608 336 608 464 0
w 608 464 640 464 0
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w 576 288 576 352 0
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w 576 480 640 480 0
w 800 416 544 416 0
w 544 416 544 240 0
w 544 240 640 240 0
w 544 240 544 112 0
w 544 112 640 112 0
w 544 416 544 496 0
w 544 496 640 496 0
w 800 544 512 544 0
w 512 544 512 368 0
w 512 368 640 368 0
w 512 368 512 224 0
w 512 224 640 224 0
w 512 224 512 80 0
w 512 80 640 80 0
c 688 144 752 144 0 0.00001 4.275735888810727
w 688 128 688 144 0
w 752 128 752 144 0
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5
  • 1
    \$\begingroup\$ A graphical schematic would be more helpful for understanding your problem than a netlist. \$\endgroup\$
    – The Photon
    Jan 3, 2017 at 1:27
  • \$\begingroup\$ Consider that your simulator (whichever you're using) may simply not be capable of simulating that kind of circuit. Using a small-value cap to force a F/F to come up in a known state is "mostly reliable", but there are edge-cases that can catch you out. \$\endgroup\$ Jan 3, 2017 at 1:31
  • \$\begingroup\$ @the-photon I've uploaded an image \$\endgroup\$ Jan 3, 2017 at 1:49
  • \$\begingroup\$ the photon should delete his incorrect answer @RyanJenkin click my Proof link ..approve Java, then Reset The metastable condition is a single stage inverting feedback metastable infinite oscillator ( in reality limited by real latency) \$\endgroup\$ Jan 3, 2017 at 3:59
  • \$\begingroup\$ @RyanJenkin LEDs need more current to turn ON so I changed to 220 series, also Sim uses Ideal parts , no ESR or latency so you must add. Edit Gate to change number of inputs and Options> small grid to draw small gates... Ctrl+click to drag parts , scale rotate etc \$\endgroup\$ Jan 3, 2017 at 4:09

2 Answers 2

1
\$\begingroup\$

This is how everyone's specs ( or question) should be written as follows:

A Hierarchical Input Process Output or HIPO descrption. Same for documenting software routines. INs OUTs and FUNCTIONS

  • Inputs: 4 momentary SET switches (normally=0)
  • Process: Each switch acts as a SET to it's own Register AND a RESET to all others, thus creating an exclusive N bit SET function to Register
    • This is an async. latch function, not a edge-triggered synchronous type.
    • Initial Condition options; 1000, 0100, 0010, 0001, or 1111. illegal=0000.
      • IN=0000 does not converge to steady state
    • OUTPUT Latch follows INPUT exclusive switch with last switch pressed
    • If multiple inputs are pressed ( multiple outputs occur in same sequence but REMEMBERS Last SWITCH INPUT released with Exclusive Output.
  • Outputs: 4 Bit Latch with exclusive state ( only 1 output SET after nano delay )

Proof of Concept in slow motion ( 0.1ns per second )

https://goo.gl/F3H7PT ( Needs Java Approval in browser )

enter image description here

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  • \$\begingroup\$ Does your circuit demonstrate the metastable condition or how to set the initial state? \$\endgroup\$ Jan 3, 2017 at 4:47
  • \$\begingroup\$ Initial condition is all outputs =1 (forced by RC) and switch=1. it is more accurately described as a conditional Astable condition with zero latency between NAND outputs and OR/NAND inputs thus infinite frequency. I attempted to slow down the output with RC filter but without hystereis it still oscillates beyond resolution of simulator even when 0.001ps was tried. \$\endgroup\$ Jan 3, 2017 at 5:29
  • \$\begingroup\$ Clever simulation trick, but in the real world it fails as soon as there is not exactly the same time constant in the different feedback paths. Change your added capacitors to 10.0, 10.1, 10.2 and 10.3 pF, for example, and you'll no longer have an oscillator. \$\endgroup\$
    – The Photon
    Jan 3, 2017 at 5:45
  • \$\begingroup\$ But you do have a funny 4-output latch like OP expected to have. \$\endgroup\$
    – The Photon
    Jan 3, 2017 at 5:47
  • \$\begingroup\$ I can get one, but his specs are not stated, just the question. \$\endgroup\$ Jan 3, 2017 at 6:04
0
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In the given circuit, the capacitor should work in most cases to bring the circuit up in the expected state.

But this could be defeated, for example by ramping Vdd up very slowly during power up. Then the circuit could come on in a random state.

A more straightforward, and foolproof, way to get the circuit into a preferred state is simply to close one of the input switches during or after power up and then release it.

does the "convergence failed" error highlight a real problem with my circuit,

Convergence failure in this circuit might come from trying to solve this as a DC circuit; that is, ignoring the capacitor.

In reality, even if the capacitor were not present, this circuit will reach some stable state after power up, you just would not be able to predict which output will end up in the high state.

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  • \$\begingroup\$ disagree, its a ring osc race condition with zero prop delay (ideal gate) \$\endgroup\$ Jan 3, 2017 at 3:24
  • \$\begingroup\$ @TonyStewart.EEsince'75, Show me a design for a ring oscillator with an even number of stages and I'll reconsider. \$\endgroup\$
    – The Photon
    Jan 3, 2017 at 3:36
  • \$\begingroup\$ 1 stage, proof self evident in my falstad link .. press reset and output stays at Vcc/2 and oscillates \$\endgroup\$ Jan 3, 2017 at 4:00
  • \$\begingroup\$ @Tony, I don't see any feedback from one stage to itself in OP's circuit. And your link just says "You need a Java-enabled browser to view this content". \$\endgroup\$
    – The Photon
    Jan 3, 2017 at 4:01
  • \$\begingroup\$ correct get one I improved his design , but kept same logic \$\endgroup\$ Jan 3, 2017 at 4:01

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