I was wondering if it is possible to automatically generate a schematic from some higher-level description (CPU ==> RAM, etc) of a circuit? And whether there are tools that can do that?
There are such tools, e.g Altera Qsys. You tell the tool which blocks you want to include (CPUs, memory, peripherals) and define a memory map. The tool then generates the system logic using the interface bus of your choice (Avalon, AMBA, etc.) Typically, some sort of include files are generated as well, to facilitate software development.
Some VHDL tools do offer schematic diagram generators, and they are generally appalling. They are logically correct of course, but completely ineffective as an aid to understanding.
It's not surprising when you consider how difficult it is to tell an electronics noob what constitutes a good schematic. Once you have +ve up and signals left to right, there's still plenty of scope to make a difference between ugly/useless and well-designed/useful. And that's a human you're trying to tutor, not a program you're trying to write.
In my experience, engineers only get one printout of the auto generated schematic. After that, they do their own high level block diagram in powerpoint, improve their choice of names, and then rely on the blocks being small enough to understand the VHDL.