I am trying to make a simple bit alternator for the purpose of learning how to use verilog for FGPA design and how to simulate in modelsim. Here is my code:
module top ( input wire clk, output reg data ); initial begin data = 1'b1; end always @ (posedge clk) begin data = ~data; end endmodule
Here is my attempt at simulating the program in modelsim. I set the clock period to 100ps and gave the data/clock an initial value of 1, yet the waveform shows strange results.
Perhaps I'm not using modelsim correctly? or is something missing from my code? Any help would be appreciated!