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I am trying to make a simple bit alternator for the purpose of learning how to use verilog for FGPA design and how to simulate in modelsim. Here is my code:

module top (
    input wire clk,
    output reg data
);

initial begin
    data = 1'b1;
end

always @ (posedge clk)
begin 
    data = ~data;
end
endmodule

Here is my attempt at simulating the program in modelsim. I set the clock period to 100ps and gave the data/clock an initial value of 1, yet the waveform shows strange results.

enter image description here

enter image description here

Perhaps I'm not using modelsim correctly? or is something missing from my code? Any help would be appreciated!

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  • \$\begingroup\$ Your clock looks strange, how are you generating it? \$\endgroup\$ – Greg Jan 6 '17 at 23:01
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    \$\begingroup\$ "I set the clock period to 100ps" How? Show us your testbench code. \$\endgroup\$ – Tom Carpenter Jan 6 '17 at 23:02
  • \$\begingroup\$ Haven't learned how to make timing testbench code yet. I manually initialized things using "force" and dragged variables to the wave tab. \$\endgroup\$ – Sumeet Batra Jan 6 '17 at 23:07
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    \$\begingroup\$ I'd highly suggest you use a Verilog testbench file. \$\endgroup\$ – Tom Carpenter Jan 6 '17 at 23:12
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    \$\begingroup\$ Show your testbench code. Don`t forget to add delays in the TB code between clock transitions or maybe try zooming more \$\endgroup\$ – Elbehery Jan 7 '17 at 10:20
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Try with this sequence of commands:

restart -f

force -drive sim:/top/clk 0 0

force -freeze sim:/top/clk 1 0, 0 {50 ps} -r 100

run 10ns

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  • \$\begingroup\$ This worked, thank you. I am going to accept this as the answer, but was hoping if you could point me to any tutorials on creating altera fpga specific modelsim testbenches for synchronous programs. Doing this for every project I make, especially as they get more complex, will get very tedious. \$\endgroup\$ – Sumeet Batra Jan 11 '17 at 22:05
  • \$\begingroup\$ Of course. You must start using test benches. I have several examples of code and testbenches at my site dedicated to FPGAs, which you can find visiting my profile. However, i use VHDL. I also recommend you warmly to explore Altera site where you will find a lot of code examples and tutorials. \$\endgroup\$ – Claudio Avi Chami Jan 12 '17 at 8:36

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