# Verilog Synchronous bit alternator (Quartus/Modelsim) - Altera FPGA

I am trying to make a simple bit alternator for the purpose of learning how to use verilog for FGPA design and how to simulate in modelsim. Here is my code:

module top (
input wire clk,
output reg data
);

initial begin
data = 1'b1;
end

always @ (posedge clk)
begin
data = ~data;
end
endmodule


Here is my attempt at simulating the program in modelsim. I set the clock period to 100ps and gave the data/clock an initial value of 1, yet the waveform shows strange results.

Perhaps I'm not using modelsim correctly? or is something missing from my code? Any help would be appreciated!

• Your clock looks strange, how are you generating it? – Greg Jan 6 '17 at 23:01
• "I set the clock period to 100ps" How? Show us your testbench code. – Tom Carpenter Jan 6 '17 at 23:02
• Haven't learned how to make timing testbench code yet. I manually initialized things using "force" and dragged variables to the wave tab. – Sumeet Batra Jan 6 '17 at 23:07
• I'd highly suggest you use a Verilog testbench file. – Tom Carpenter Jan 6 '17 at 23:12
• Show your testbench code. Don`t forget to add delays in the TB code between clock transitions or maybe try zooming more – Elbehery Jan 7 '17 at 10:20