# Transmission line simulation in LTSpice? How to model a CMOS input?

I am trying to simulate the effect of a PCB trace on a clock signal with LTSpice, see the following pictures:

In my quick and dirty setup, the clock receiver is the resistor Rin. I the real world, it is a DAC with a CMOS input. Is there an easy way to model such an input in LTSpice? Is the resistor accurate enough?

• a sniff of capacitance would be better, 5pF give or take. – Neil_UK Jan 7 '17 at 21:17
• R only? NO Cin depends on family of CMOS and Vdd, of which there are dozens. All CMOS is rated at a fixed load pF which, due to RdsON of output driver limits the slew rate. So which family? More important is to simulate a track w/g dimension ratio to ground with related Zo and length? This gives the 2nd order response to ringing, Not RdsOn*Ciss which is 1st order . ok? – Tony Stewart Sunnyskyguy EE75 Jan 7 '17 at 22:02
• (also in real scopes, the length of probe ground and L value. – Tony Stewart Sunnyskyguy EE75 Jan 7 '17 at 22:07
• What's wrong with a plain NMOS/PMOS? – a concerned citizen Jan 8 '17 at 7:09

$Z_0 = \sqrt{\frac{L}{C}} = \sqrt{\frac{1874,79 \text{nH}}{56,98 \text{pF}}} = 181,3907313029 \Omega$